Supported MATLAB Data Types, Operators, and Control Flow Statements

When you generate HDL and SystemC code from your MATLAB^® algorithm, use the data types, operators, and control flow statements that HDL Coder™ supports.

Supported Data Types

HDL Coder does not support cell arrays and Inf data types. This table shows the supported subset of MATLAB data types.

Types	Supported Data Types	Restrictions
Integer	uint8, uint16, uint32, uint64 int8, int16, int32, int64	In Simulink®, MATLAB Function block ports must use numeric types sfix64 or ufix64 for 64-bit data.
Real	double single	HDL code generated with double or single data types in your MATLAB code can be used for simulation, but is not synthesizable. You can generate synthesizable code when you use these data types in your Simulink model. For more information, see: Simulink Blocks Supported by Using Native Floating Point Generate Target-Independent HDL Code with Native Floating-Point Signal and Data Type Support Real data types are not supported for SystemC code generation.
Character	char	–
Logical	logical	–
Fixed point	Scaled (binary point only) fixed-point numbers Custom integers (zero binary point)	Fixed-point numbers with slope (not equal to 1.0) and bias (not equal to 0.0) are not supported. Maximum word size for fixed-point numbers is 128 bits.
Vectors	unordered {N} row {1, N} column {N, 1}	The maximum number of vector elements allowed is 2^32. Before a variable is subscripted, it must be fully defined.
Matrices	{N, M}	Matrices are supported in the body of the design algorithm and as inputs to the top-level design function.
Structures	struct	Arrays of structures are not supported. For the FPGA Turnkey and IP Core Generation workflows, structures are supported in the body of the design algorithm, but are not supported as inputs to the top-level design function. Structures are not supported as inputs and outputs at the top-level DUT ports for SystemC code generation.
Enumerations	enumeration	Enumeration values must be monotonically increasing. If your target language is Verilog®, all enumeration member names must be unique within the design. Enumerations at the top-level DUT ports are not supported with the following workflows or verification methods: IP Core Generation workflow FPGA Turnkey workflow FPGA-in-the-Loop HDL Cosimulation SystemC Code Generation Workflow Enumerations are not supported as inputs and outputs at the top-level DUT ports for SystemC code generation.

Global variables are not supported for HDL and SystemC code generation.

Supported Operators

Note

HDL and SystemC code generated for large vector and matrix inputs to arithmetic operations can result in inefficient code. The code for these operators is not automatically pipelined.

Arithmetic Operators

Operation	Operator Syntax	Equivalent Function	Restrictions
Binary addition	A+B	plus(A,B)	Neither A nor B can be data type logical.
Matrix multiplication	A*B	mtimes(A,B)	HDL code generated for matrix arithmetic operations is not pipelined, and can result in inefficient code.
Arraywise multiplication	A.*B	times(A,B)	Neither A nor B can be data type logical.
Matrix power	A^B	mpower(A,B)	A and B must be scalar, and B must be an integer. HDL code generated for matrix arithmetic operations is not pipelined, and can result in inefficient code.
Arraywise power	A.^B	power(A,B)	A and B must be scalar, and B must be an integer.
Complex transpose	A'	ctranspose(A)	–
Matrix transpose	A.'	transpose(A)
Matrix concat	[A B]	None	–
Matrix index	A(r c)	None	Before you use a variable, you must fully define it.

Logical Operators

Operation	Operator Syntax	M Function Equivalent	Notes
Logical And	A&B	and(A,B)	–
Logical Or	A|B	or(A,B)	–
Logical Xor	A xor B	xor(A,B)	–
Logical And (short circuiting)	A&&B	N/A	Use short circuiting logical operators within conditionals.
Logical Or (short circuiting)	A||B	N/A	Use short circuiting logical operators within conditionals.
Element complement	~A	not(A)	–

Relational Operators

Relation	Operator Syntax	Equivalent Function
Less than	A<B	lt(A,B)
Less than or equal to	A<=B	le(A,B)
Greater than or equal to	A>=B	ge(A,B)
Greater than	A>B	gt(A,B)
Equal	A==B	eq(A,B)
Not equal	A~=B	ne(A,B)

Control Flow Statements

HDL Coder supports the following control flow statements and constructs with restrictions.

Control Flow Statement	Restrictions
for	Do not use for loops without static bounds. Do not use the & and | operators within conditions of a for statement. Instead, use the && and || operators. HDL Coder does not support nonscalar expressions in the conditions of for statements. Instead, use the all or any functions to collapse logical vectors into scalars.
if	Do not use the & and | operators within conditions of an if statement. Instead, use the && and || operators. HDL Coder does not support nonscalar expressions in the conditions of if statements. Instead, use the all or any functions to collapse logical vectors into scalars.
switch	The conditional expression in a switch or case statement must use only: uint8, uint16, uint32, int8, int16, or int32 data types Scalar data If multiple case statements make assignments to the same variable, the numeric type and fimath specification for that variable must be the same in every case statement.

The following control flow statements are not supported:

• while

• break

• continue

• return

• parfor

Avoid using the following vector functions, as they may generate loops containing break statements:

• isequal

• bitrevorder