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Configure the PLL and sampling rate of ADC tile

Since R2020b


configureADCTile(rfDataConverter,tileId,PLLSrc,PLLRefClk,samplingRate) configures the source and reference clock of the phase-locked loop (PLL) and sampling rate of the specified ADC tile.

Input Arguments

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RF data converter, specified as an soc.RFDataConverter object. Via Ethernet, this object connects the host computer to the RF data converter on the connected SoC device. Use the object functions and properties of this object to configure the RF data converter.

Identifier of the RF-ADC tile connected to the programmable logic, specified as 0, 1, 2, or 3. Available options for the RF-ADC tile ID vary according to the specified RFSoC device. A tile contains several ADCs, accessible as channels, and several shared timing units, including a clock and PLL.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Source clock signal of the PLL in the RF-ADC tile, specified as "Internal" or "External LMK/LMX". The source clock signal can come from either the clock in the tile or the external source.

Data Types: char | string

Frequency of the reference clock to the PLL, specified as a positive scalar. This reference clock frequency drives the PLL in the RF-ADC tile.

Data Types: double

Sampling rate in MHz, specified as a positive scalar.

Data Types: double

Version History

Introduced in R2020b