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Filter Design HDL Coder
Generate HDL code for fixed-point filters
Filter Design HDL Coder™ generates synthesizable, portable VHDL® and Verilog® code for implementing fixed-point filters designed with MATLAB® on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.
Getting Started
Learn the basics of Filter Design HDL Coder
Code Generation Fundamentals
HDL code generation startup, language selection, HDL code generation scripts
Filter Configuration Options
Single rate, multirate, cascaded, other advanced digital filters
Optimization
Resource usage, clock speed, chip area, latency
Customization
File names and locations, identifiers and comments, ports and resets, HDL language constructs
Verification
HDL test bench generation, and cosimulation with third party EDA tools
Synthesis and Workflow Automation
Compilation, simulation, and synthesis script generation
