Get Started with HDL Verifier
R2026bHDL Verifier™ enables you to reuse your system-level design environment in your HDL design and verification environment for FPGAs and ASICs. You can test and verify RTL designs against golden reference models in MATLAB® and Simulink®, debug designs using HDL simulators, and generate testbenches and verification IP.
Use HDL cosimulation to verify ASICs and FPGAs with testbenches that run in MATLAB and Simulink with RTL code that runs in your HDL simulator. You can generate SystemVerilog DPI-C models from MATLAB, Simulink, and Simscape™ to perform functional verification using digital and mixed-signal simulation in HDL simulators. You can also generate Universal Verification Methodology (UVM) components from MATLAB and Simulink for production workflows or generate SystemC™ TLM 2.0 Transaction Level Models (TLMs) from Simulink models for virtual platform simulation. All these capabilities are compatible with existing HDL code and code generated by HDL Coder™.
Tutorials
- Verify HDL Module with MATLAB Testbench
This tutorial guides you through the basic steps to set up an HDL Verifier™ application that uses MATLAB® to verify a simple HDL design. - Verify HDL Module with Simulink Testbench
Set up an HDL Verifier session that uses Simulink to verify a simple VHDL® model. - Get Started with Cosimulation Wizard for MATLAB System Object
Using HDL Verifier™, you can set up cosimulation between MATLAB® or Simulink® and an HDL simulator. - Verify Raised Cosine Filter Design Using Simulink
Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation. - Choose a Test Bench for Generated HDL Code (HDL Coder)
Select a generated test bench. - Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
HDL Cosimulation
HDL Code Import
Verify Generated HDL Code with HDL Workflow Advisor (requires HDL Coder license)
About HDL Verification
- HDL Cosimulation
The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
- TLM Component Generation
HDL Verifier lets you create a SystemC Transaction Level Model (TLM) that can be executed in any OSCI-compatible TLM 2.0 environment, including a commercial virtual platform.
- SystemVerilog DPI Component Generation
HDL Verifier works with Simulink Coder™ or MATLAB Coder to export a subsystem as generated C code inside a SystemVerilog component with a Direct Programming Interface (DPI).
Featured Examples
Get Started with Cosimulation Wizard for MATLAB System Object
Using HDL Verifier™, you can set up cosimulation between MATLAB® or Simulink® and an HDL simulator. The Cosimulation Wizard is a graphical user interface (GUI) that takes HDL code as input and generates a cosimulation block or System object™ as output. The System object allows cosimulating HDL within MATLAB, and the block allows cosimulating HDL within Simulink.
Get Started with Simulink HDL Cosimulation
Set up an HDL Verifier™ application using the Cosimulation Wizard in the Simulink® environment.
Comparing HDL and Simulink Code Coverage Using Cosimulation
Achieve complete code coverage of an HDL cruise controller design using Simulink® and an HDL Simulator.
Get Started with SystemVerilog DPI Component Generation
Generate a SystemVerilog DPI component from a proportional-integral-derivative (PID) controller in a Simulink® model and how to export the component to an HDL simulator.
Get Started with MATLAB Based SystemVerilog DPI Generation
Generate a SystemVerilog DPI component for a programmable square-wave generator written in MATLAB®, and export it to an HDL simulator.
Videos
HDL Verifier Overview
Test and verify Verilog® and VHDL designs for FPGAs, ASICs, and SoCs with HDL Verifier. Verify RTL with testbenches running in MATLAB or Simulink using cosimulation with HDL simulators. Use these same testbenches
with FPGA and SoC development boards to verify HDL implementations in
hardware.
