Composite data type

How the SystemVerilog ports are generated when your Simulink model includes a port which is a Nonvirtual bus or a complex data type

Model Configuration Pane: SystemVerilog DPI / SystemVerilog Ports

Description

Choose how the SystemVerilog ports are generated when your Simulink^® model includes a port which is a Nonvirtual bus or a complex data type. Choose between interfaces with struct data types or flattened SystemVerilog ports.

Settings

Flattened (default) | Structure

Default: Flattened

Flattened

Generate a SystemVerilog module with flattened ports.

Structure

Generate a SystemVerilog module with struct data type ports.

Programmatic Use

Parameter: DPICompositeDataType

Type:

Values:Flattened |Structure

Default: Flattened

Version History

Introduced in R2013b