The Fractional Clock Divider with DSM subsystem
block consists of four delta sigma modulators of orders one to four encapsulated
inside the DSM Selector variant subsystem. The output of the DSM selector drives a
Single Modulus
Prescaler block. Given the **Delta Sigma Modulator
order**, corresponding delta sigma modulator gets activated.

The modulator order defines the range over which the *N* counter
value is varied. For an *n*th-order delta sigma modulator,
*N* is varied over 2^{n} different
values. This variation is achieved by integrating the changes in the fractional part
(*.FF*) from the previous cycle and quantizing the differential
changes.

The general form of the transfer function for an nth order delta sigma modulator
is:

$$Y(z)=X(z)+E(z)\xb7{(1-{z}^{-1})}^{\text{n}}$$

where

*Y(z)* = Output of the modulator

*X(z)* = Input the modulator

*E(z)* = Quantization error

*E(z)* is calculated by subtracting the value of input
*X(z)* in the present cycle from its value in the previous
cycle. In other words, *E(z)* is a form of a digital highpass
filtering.

The higher-order modulators reduce the primary fractional spurs by alternating
*N* over a larger range of integer values. As a result, the
fractional spurs are pushed to higher frequencies in the frequency spectrum and can
be filtered more effectively by the loop filter in a PLL system.

For example, if the third-order delta sigma modulator is activated,
*N* is varied over 8 different values, which can range from
(*N*-3) to (*N*+4).

**Delta Sigma Modulator Sequence**

Modulator Order | Range | DSM Sequence |

1st | 0, 1 | *N*, *N*+1 |

2nd | -1, 0, 1, 2 | *N*-1, *N*,
*N*+1, *N*+2 |

3rd | -3, -2, -1, 0, 1, 2, 3, 4 | *N*-3, *N*-2, …,
*N*+4 |

4th | -7, -6, …, 7, 8 | *N*-7, *N*-6, …,
*N*+8 |