CMOS OR
R2026bBehavioral model of CMOS OR gate
CMOS OR block
To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.
Libraries:
Simscape /
Electrical /
Integrated Circuits /
Logic
Description
The CMOS OR block represents a CMOS OR logic gate behaviorally:
The block output logic level is
HIGHif the logic levels of any of the gate inputs are 1.The block output logic level is
LOWotherwise.
The block determines the logic levels of the gate inputs as follows:
If the gate voltage is greater than the threshold voltage, the block interprets the input as logic 1.
Otherwise, the block interprets the input as logic 0.
The threshold voltage is the voltage value at midpoint between the High level input voltage parameter value and the Low level input voltage parameter value.
Note
To improve simulation speed, the block does not model all the internal individual MOSFET devices that make up the gate. See Assumptions and Limitations for details.
The block models the gate as follows:
The gate inputs have infinite resistance and finite or zero capacitance.
The gate output offers a selection of two models:
LinearandQuadratic. For more information, see Selecting the Output Model for Logic Blocks. Use the Output current-voltage relationship parameter to specify the output model.You can specify propagation delay for both output models. For
Linearoutput, the block sets the value of the gate output capacitor such that the resistor-capacitor time constant equals the Propagation delay parameter value. ForQuadraticoutput, the gate input demand is lagged to approximate the Propagation delay parameter value.
The block initial conditions depend on the output model selected:
For
Linearmodel, the high initial condition corresponds to the High level output voltage parameter value,V_OH, and the low initial condition corresponds to the Low level output voltage parameter value,V_OL.For
Quadraticmodel, the high initial condition is a value close to the Supply voltage parameter value,Vcc, and the low initial condition is close to0.
The block output voltage depends on the output model selected:
For
Linearmodel, output high is the High level output voltage parameter value, and output low is the Low level output voltage parameter value.For
Quadraticmodel, the output voltage for High and Low states is a function of the output current, as explained in Quadratic Model Output and Parameters. For zero load current, output high is Vcc (the Supply voltage parameter value), and output low is zero volts.
Plot Input and Output Waveforms
You can plot the input and output voltage waveforms of the CMOS OR block without building a complete model. Use the plots to explore the impact of your parameter choices on device characteristics. If you parameterize the block from a data sheet, you can compare your plots to the data sheet to check that you parameterized the block correctly. If you have a complete working model but do not know which manufactured part to use, you can compare your plots to data sheets to help you decide.
To plot the basic characteristics, in the Utilities section, click the Plot button next to the Basic characteristics parameter. (since R2026a)
Before R2026a: right-click the block and select Electrical > Basic Characteristics from the context menu.
Note
The plots you create using the Basic characteristics parameter do not show the effect of the Propagation delay parameter on the output voltage of logic blocks.
For more information, see Plot Basic Input-Output Voltage Characteristics of Logic Gates.
Assumptions and Limitations
The block does not model the internal individual MOSFET devices that make up the gate
(except for the final MOSFET pair if you select the Quadratic
option for the Output current-voltage relationship parameter). This
limitation has the following implications:
The block does not accurately model the gate's response to input noise and inputs that are around the logic threshold voltage.
The block does not accurately model dynamic response.
Circuits that involve a feedback path around a set of logic gates may require a nonzero propagation delay to be set on one or more gates.
