Model Verification

R2026b

Bloques que comprueban que las señales estén dentro de los límites especificados durante la simulación, como Assertion y Check Static Range

Use bloques de la biblioteca Model Verification para comprobar que las señales cumplan los límites y las condiciones especificados durante la simulación. Cuando una señal infringe una condición de verificación, el bloque puede mostrar una advertencia, detener la simulación o ambas, lo que permite detectar errores de diseño en una fase temprana sin escribir scripts de prueba separados.

Para añadir bloques de esta biblioteca al modelo, consulte Add Blocks to Models.

Bloques

	Assertion	Check whether signal is zero
	Check Dynamic Gap	Check that gap of possibly varying width occurs in range of signal's amplitudes
	Check Dynamic Range	Check that signal falls inside range of amplitudes that varies from time step to time step
	Check Static Gap	Check that gap exists in signal's range of amplitudes
	Check Static Range	Check that signal falls inside fixed range of amplitudes
	Check Discrete Gradient	Check that absolute value of difference between successive samples of discrete signal is less than specified value
	Check Dynamic Lower Bound	Check that one signal is always less than another signal
	Check Dynamic Upper Bound	Check that one signal is always greater than another signal
	Check Input Resolution	Check that input signal has specified resolution
	Check Static Lower Bound	Check that signal is greater than (or optionally equal to) static lower bound
	Check Static Upper Bound	Check that signal is less than (or optionally equal to) static upper bound