sldvoptions
Create design verification options object
Description
Examples
Create an Options Object
Create an options object and set several parameters.
Create an opts
option for the
sldvdemo_cruise_control
model:
opts = sldvoptions; opts.AutomaticStubbing = 'on'; opts.Mode = 'TestGeneration'; opts.ModelCoverageObjectives = 'MCDC'; opts.ReportIncludeGraphics = 'on'; opts.SaveHarnessModel = 'off'; opts.SaveReport = 'off'; opts.TestSuiteOptimization = 'LongTestcases';
Create Standalone Options Object using deepCopy
Get the options object for the
sldvdemo_cruise_control
model. You can use
deepCopy
method if you want to create a standalone
version of sldvoptions
but would like to start with copy of
options from the model configuration set.
Open the model sldvdemo_cruise_control
in command
prompt:
openExample('sldv/CruiseControlTestGenerationExample',... 'supportingFile', 'sldvdemo_cruise_control'); optsModel = sldvoptions(bdroot); optsCopy = optsModel.deepCopy; optsCopy.MaxProcessTime = 120;
Input Arguments
model
— Name or handle to a model
character vector | string scalar
Name or handle to a Simulink® model, specified as a character vector or string scalar.
Output Arguments
options
— Options for design verification
character vector
This table lists the parameters that comprise a Simulink Design Verifier™ options object.
Parameter | Description | Values | |||||
---|---|---|---|---|---|---|---|
| Specify an absolute value for tolerance in relational boundary tests. | double
| |||||
| Specify whether Assertion blocks in your model are enabled or disabled. |
| |||||
| Specify whether the software ignores unsupported blocks and functions and proceeds with the analysis. |
| |||||
| Specify whether the software replaces blocks in a model before its analysis. When set to
|
| |||||
| Specify a folder and file name for the model that is the result after applying block replacement rules. This parameter is enabled when
| character array
| |||||
| Specify a list of block replacement rules that execute before its analysis. This parameter
is enabled when | character array
| |||||
| Extra options for analyzing S-functions that have been compiled to be compatible with Simulink Design Verifier. See Support Limitations and Considerations for S-Functions and C/C++ Code. | character array
| |||||
| Specify a folder and file name for the file that contains data about satisfied coverage objectives. This parameter is enabled when
| character array
| |||||
| For test generation and design error detection analysis, specify whether to ignore objectives stored in coverage filter file. When set to on, this
parameter enables
|
| |||||
| For test generation and design error detection analysis, specify a name for the coverage filter file that contains objectives to exclude from analysis. This parameter is enabled when
| character array
| |||||
| Specify a folder and file name for the MAT-file
that contains the data generated during the analysis,
stored in an | character array
| |||||
| Defect Checker helps you to effortlessly check the components throughout the development phase for common and critical design errors such as division by zero, integer overflow, dead logic, and array out of bounds. |
| |||||
| Specify whether to check that the intermediate and output signals in your model are within the range of specified minimum and maximum constraints. |
| |||||
| Specify whether Simulink Design Verifier software generates test cases that consider specified minimum and maximum values as constraints for input signals in your model. |
| |||||
| Specify whether to analyze your model for active logic. This parameter is enabled only if
|
| |||||
| Specify whether to analyze your model for block input range violations. For more information, see Specified block input range violations. |
| |||||
| Specify whether to analyze your model for dead logic. |
| |||||
| Specify whether to analyze your model for division-by-zero errors. |
| |||||
| Specify whether to analyze your model for data store access violations. |
| |||||
DetectHISMViolationsHisl_0002 | Specify whether to check the usage of
|
| |||||
DetectHISMViolationsHisl_0003 | Specify whether to check the usage of Square Root operations with inputs that can be negative. |
| |||||
DetectHISMViolationsHisl_0004 | Specify whether to check the usage of
|
| |||||
DetectHISMViolationsHisl_0028 | Specify whether to check the usage of Reciprocal Square Root blocks with inputs that can go zero or negative. |
| |||||
| Specify whether to analyze your model for non-finite and NaN floating-point values. |
| |||||
| Specify whether to analyze your model for integer and fixed-point data overflow errors. |
| |||||
| Specify whether to analyze your model for out of bounds array access errors. |
| |||||
| Specify whether to analyze your model for subnormal floating-point values. |
| |||||
| Display the report that the Simulink Design Verifier analysis generates after completing its analysis. This parameter is enabled when
|
| |||||
| Specify a folder and file name for the MAT-file that contains the logged test case data. This parameter is enabled when
| character array
| |||||
| Extend the Simulink Design Verifier analysis by importing test cases logged from a harness model or a closed-loop simulation model. When set to This
parameter is enabled when |
| |||||
| Specify a folder and file name for the harness model. This parameter is enabled when
| character array
| |||||
| Specify the type of the Inputs block for the harness model. This parameter is enabled
when |
| |||||
| Specify to analyze the model, ignoring satisfied
coverage objectives, as specified in
|
| |||||
| Ignore the coverage objectives satisfied by the
logged test cases in
This
parameter is enabled when |
| |||||
| Specify generation of test cases that satisfy relational boundary objectives. |
| |||||
| Specify whether the software makes its output file names unique by appending a numeric suffix. |
| |||||
| Specify the maximum time (in seconds) that Simulink Design Verifier spends analyzing a model. You can set the value of maximum analysis time to the value that you are willing to provide to the analysis. You can also stop the analysis at any time. | int32
| |||||
| Specify the maximum number of simulation steps when attempting to satisfy a test objective. The
analysis uses the To achieve the best
performance, set the When you set the
This parameter is enabled when
| int32
| |||||
| Specify the maximum number of simulation steps over which the software searches for property violations. This parameter is enabled
when | int32
| |||||
| Specify the analysis mode. |
| |||||
| Specify the type of model coverage to achieve. When
This parameter is enabled when
|
| |||||
| Use a Model block to reference the model to run in the harness model. |
| |||||
|
| character array
| |||||
| Specify how to configure parameters during Simulink Design Verifier analysis. |
| |||||
| Specify a MATLAB® function that defines parameter configurations for a model. This parameter
is enabled when | character array
| |||||
| Specify whether Proof Assumption blocks in your model are enabled or disabled. |
| |||||
| Specify the strategy for proving properties. |
| |||||
| Specify whether to use random values instead of zeros for input signals that have no impact on test or proof objectives. |
| |||||
| Specify whether to rebuild the model representation for Simulink Design Verifier analysis. |
| |||||
| Specify whether to run additional analysis to reduce instances of rational approximation. |
| |||||
| Specify a relative value for tolerance to be used in relational boundary tests. | double | |||||
| Specify a folder and file name for the analysis report. This parameter is enabled when
| character array
| |||||
| Includes screen shots of properties in the report. Valid only in property-proving mode. This
parameter is enabled when |
| |||||
| Simulate the model by using test case signals and include the output values in the Simulink Design Verifier data file. |
| |||||
| Create a harness model generated by the Simulink Design Verifier analysis. When
When set to
|
| |||||
| Generate and save a Simulink Design Verifier report. When this parameter is
set to When set to
|
| |||||
| Enable support for S-functions that have been compiled to be compatible with Simulink Design Verifier. See Support Limitations and Considerations for S-Functions and C/C++ Code. |
| |||||
| Specify whether to use strict propagation conditions for enhanced MCDC analysis. This
parameter is enabled when |
| |||||
| Specify whether Test Condition blocks in your model are enabled or disabled. This parameter is
enabled when |
| |||||
| Specify the test generation target as model, code generated as top model, or code generated as model reference. | character array
| |||||
| Specify whether Test Objective blocks in your model are enabled or disabled. This parameter is
enabled when |
| |||||
| Specify the optimization strategy to use when generating test cases. This parameter is
enabled when If
you analyze your model by using the
|
| |||||
| Specify whether to validate test cases or counterexamples with parallel computing. This option requires a Parallel Computing Toolbox™ license. |
|
Alternatives
To set the analysis options, on the Design Verifier tab, in the Prepare section, from the drop-down menu for the mode settings, click Settings.
Version History
Introduced in R2007aR2024b: Version History
Simulink
Design Verifier analysis produces an error when you set the harnessSource
option to Signal Builder block.
See Also
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