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Using Existing Coverage Data During Subsystem Analysis

This example shows how Simulink® Design Verifier™ can target its analysis to a single subsystem within a continuous-time closed-loop simulation and generate test cases for missing coverage in that subsystem.

The example starts by measuring the coverage of a subsystem in a closed-loop simulation model. Simulink Design Verifier finds new test cases that achieve the missing coverage of the subsystem.

Measure Coverage of the Subsystem

The sldvdemo_autotrans model is a closed-loop simulation model. The subsystem ShiftLogic is a Stateflow® chart and represents the controller part of this model. Test cases designed in the Signal Editor block ManeuversGUI drive the closed-loop simulation. You can use the cvtest (Simulink Coverage) and cvsim (Simulink Coverage) functions to measure the model coverage achieved for this subsystem inside the closed-loop simulation model. In this example, specifying the input to cvtest as a path to the subsystem rather than to the model name results in measuring the coverage for the subsystem only. Also, the second input to cvsim specifies the time interval to simulate the model and it is derived from the time range of the current pane in the block ManeuversGUI.

The cvhtml (Simulink Coverage) function produces a report that indicates that 87% Decision, 67% Condition, and 33% MCDC coverage is achieved by simulating the test case authored in the block ManeuversGUI.


test = cvtest('sldvdemo_autotrans/ShiftLogic');
test.settings.decision = 1;
test.settings.condition = 1;
test.settings.mcdc = 1;

signalEditorBlock = sldvdemo_signaleditor_block('sldvdemo_autotrans');
signalEditorTime = sldvdemo_signaleditor_DataTime(signalEditorBlock);
simulationStopTime = signalEditorTime{1,1}(end);

existingCovData = cvsim(test,[0 simulationStopTime]);
cvhtml('Existing Coverage', existingCovData);

Find Test Cases for Missing Coverage

To use existing coverage data during test generation, save existing coverage data to a .cvt coverage data file. You can use existing coverage data by specifying the coverage data path in the Coverage data file parameter and setting Ignore objectives satisfied in existing coverage data parameter to on in the Test Generation pane of Simulink Design Verifier configuration parameters.

In this example, the first input to sldvrun specifies the subsystem to analyze. Instructing Simulink Design Verifier to analyze a subsystem is beneficial when the controller part of a model needs to be tested separately or when you want to divide the analysis of a large model into smaller, manageable parts.

As you can see in the report, Simulink Design Verifier only finds test cases for the coverage objectives that are not covered in the existing coverage file. Notice that 4 coverage objectives in the subsystem ShiftLogic are proven to be unsatisfiable. This is expected because the logic inside the Stateflow chart ShiftLogic uses temporal events and since this chart updates at every sample time, usage of temporal conditions should be satisfactory. Also note that, dead code within a subsystem will always be a dead code in the model containing that subsystem.

To generate the harness model, Simulink Design Verifier extracts the contents of the subsystem ShiftLogic into a Test Unit component fed by a Signal Editor block containing the generated test cases.


opts = sldvoptions;
opts.IgnoreCovSatisfied = 'on';
opts.CoverageDataFile = 'existingcov.cvt';
opts.ModelCoverageObjectives = 'MCDC';
opts.SaveHarnessModel = 'on';
opts.SaveReport = 'on';

[status, fileNames] = sldvrun('sldvdemo_autotrans/ShiftLogic',opts,true);
[~, harnessModel] = fileparts(fileNames.HarnessModel);

Clean Up

To complete the demo, close all models and remove the saved coverage data file.