FPGA design (top-level)

View/Edit Memory Map

Click to view and edit the FPGA memory map.

Include 'MATLAB as AXI Master' IP for host-based interaction

Use host-based scripts with an integrated JTAG master on the target platform to initialize configuration registers and memory regions in the generated design. You can also use it to interact with the design while running in order to read back diagnostic information. The JTAG master can be used instead of or in addition to an embedded processor on the target platform.

Settings

Default: on, off

Include processing system

For processor-based platforms, include the processing system. The processing system must be included when using Embedded Coder^® to generate embedded software.

Settings

Default: off, on

Interrupt latency (s)

The latency from hardware asserting an interrupt to the start of the interrupt service routine.

Settings

Default: 0.00001

Register configuration clock frequency (MHz)

The system configuration clock drives the configuration register interfaces for the vendor IP cores in the system. User-authored Simulink^® IP cores will utilize the parameter below for its configuration register bus.

Settings

Default: 50

IP core clock frequency (MHz)

The clock for all Simulink-based generated HDL IP cores. A single clock drives all IP and is used for both datapath and configuration register logic.

Settings

Default: 100