Lógica
Puertas lógicas para circuitos integrados, como CMOS AND, CMOS OR y CMOS NOT
Genere una única salida lógica combinando puertas lógicas que implementan funciones booleanas.
Bloques de Simscape
| CMOS AND | Behavioral model of CMOS AND gate |
| CMOS Buffer | Behavioral model of CMOS Buffer gate |
| CMOS NAND | Behavioral model of CMOS NAND gate |
| CMOS NOR | Behavioral model of CMOS NOR gate |
| CMOS NOT | Behavioral model of CMOS NOT gate |
| CMOS OR | Behavioral model of CMOS OR gate |
| CMOS XOR | Behavioral model of CMOS XOR gate |
| D Flip-Flop | Behavioral model of D flip-flop (Desde R2024a) |
| D Latch | Behavioral model of D latch (Desde R2024a) |
| S-R Latch | Behavioral model of S-R Latch |
| Schmitt Trigger | Behavioral model of Schmitt trigger |
Temas
- Parameterizing Blocks from Datasheets
Overview of techniques used to specify block parameters to match the data from manufacturer datasheets.
- Selecting the Output Model for Logic Blocks
Explore the two output models available for logic blocks.
