Synchronous J-K Flip-Flop
This example shows how to model a J-K flip-flop from Simscape™ Electrical™ logic components. With the two switches in their default positions, both inputs to the flip-flop are set high so its output state toggles each time the clock signal goes low. Initial conditions are passed to the relevant NAND gates via the initialization commands of the block mask.
Model
Synchronous J-K Flip-Flop Subsystem
S-R Clocked Flip-Flop 1 Subsystem
Simulation Results from Simscape Logging
The plots below show the inputs and outputs for the synchronous J-K flip-flop. Both inputs to the flip-flop are set high so its output state toggles each time the clock signal goes low.