Convert analog signal on ADC input pin to digital signal
C2000 Microcontroller Blockset / Test Bench Blocks
SoC Blockset / Peripherals
The ADC Interface block simulates the analog-to-digital conversion (ADC) of a hardware board. The input analog signal gets sampled and converted into a representative digital value. A start event message signals the block to sample the input analog voltage signal. When the conversion completes, the block emits the digital representation of the analog signal and sends an event to a Task Manager (SoC Blockset) block. At this point, a connected task can execute with the new ADC sample.
start — Start analog to digital conversion
start an analog to digital conversion event
Specify an event signal to start the sampling and measurement of the analog input port signal.
analog — Analog voltage signal
Input analog voltage signal to convert into a digital measurement.
digital — SoC message data
This port sends the ADC Interface input signal data as a message to the msg input port of the ADC Read block.
wd event — Analog watchdog task event signal
This port sends a message at whenever the analog voltage signal exceeds the specified Lower threshold and Upper threshold property values. This output connects to the input of the Task Manager (SoC Blockset) block to execute the associated event-driven task to react to the over- or under-voltage input event.
To enable this port, enable the Enable analog watchdog parameter.
event — Task event signal
This port sends a message at each analog to digital signal conversion event. This output connects to the input of the Task Manager (SoC Blockset) block to execute the associated event-driven task after executing the ADC event.
To enable this port, enable the Enable interrupt parameter.
Resolution (bits) — Resolution of digital measurement
12 (default) |
An input analog signal can be represented in digital values in the form of 12 or 16 bits. The minimum value of an analog signal that can be represented in 1 bit is called resolution. One bit represents the minimum voltage resolution measurable by the ADC. The minimum voltage resolution can be determined using the following equation:
n is the Resolution
Vref is the Voltage reference
(V) parameter values.
Voltage reference (V) — Reference voltage in ADC
3 (default) |
The reference voltage determines the total voltage range that the ADC can convert into a digital value without saturating. Any voltage signal higher than this value produces the maximum possible value that can represented by the Resolution (bits) parameter.
Acquisition time (s) — Time required for ADC to capture input voltage
320e-9 (default) | positive scalar
Specify the time required for the ADC to capture the input voltage during sampling.
Conversion time (s) — Time to convert physical voltage sample to digital value
240e-9 (default) | positive scalar
Specify the required time to convert the physical voltage sample to the digital representation and output the value.
Charge/dischard time constant (s) — Charge or discharge time constant of the ADC acquisition circuit
0 (default) | nonnegative scalar
Specify the charge or discharge time constant of the ADC sample acquisition circuitry.
Number of channel — Number of channels used in multichannel sampling
1 (default) | integer in the range 1 to 16
Specify the number of channels used by the ADC module. Specifying 2 or more channels allows for either more efficient or precise measurements of the input signal.
Conversion type — Type multichannel conversion
Sequential (default) |
Select the type of multichannel conversion.
Sequential— Take sequential measurements on each ADC channel. At a new ADC event, the next channel in the sequence of channels takes a new measurement of the input signal. All other previous channel values remain unchanged. Sequential measurement improves sampling by allowing for individual conversion times of each channel to exceed the sample rate of the ADC module.
Simultaneous— Take simultaneous measurements on each ADC channel. At a new ADC event, all channels take a new measurement of the input signal, replacing the previously captured value. Simultaneous measurement allows for noise to be removed from the measurement using an average value or other filter.
Oversampling— Take oversampled measurements across the channels of the ADC. Between two timer-driven ADC events, each channel takes a time offset ADC measurement, resulting in the channels sampling the input signal evenly between the two ADC events. The resulting channel output provides an oversampled measurement of the input signal at each sample. Oversampling measurement allows for the ADC module to exceed the theoretical Nyquist sample rate of the individual channel and ADC hardware.
Enable interrupt — Option to enable interrupt event generation
enable (default) | disable
Select this parameter for the ADC Interface block to generate an interrupt following an ADC acquisition and to enable the event output port. You can connect this event port to a Task Manager (SoC Blockset) block to simulate asynchronous ADC operation.
Condition — Condition on when to trigger interrupt
Acquisition time (default) |
Acquisition + Conversion time
Select the timing condition for when to generate the ADC interrupt event. Using
Acquisition + Conversion time, the interrupt is generated
when the complete measurement is available. Using
time, the interrupt is generated prior to the measurements
availability. Allowing for the associated task to start during the conversion and
reduce execution delay in the total measurement cycle.
Enable analog watchdog — Option to enable analog watchdog interrupt event generation
off (default) | on
Select this parameter for the ADC Interface block to generate an analog watchdog interrupt following an ADC acquisition where the input voltage exceeds the specified Lower threshold and Upper threshold parameter values. Selecting this parameter also enables the wd event output port, which you can connect to a Task Manager (SoC Blockset) block to simulate task action on an over-or under-voltage event on the ADC input signal.
Lower threshold — Lower threshold watchdog trigger
0.1 (default) | real-valued scalar
Specify the lower threshold value of the analog input signal on which to trigger an analog watchdog interrupt event.
Upper threshold — Upper threshold watchdog trigger
2.9 (default) | real-valued scalar
Specify the upper threshold value of the analog input signal on which to trigger an analog watchdog interrupt event.
Interrupt latency (s) — Interrupt generation latency
0 (default) | positive scalar
Specify the time required by the ADC hardware module from the completion of the conversion to the generation of the interrupt in software.
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
To automatically generate C code for your design, and execute on an SoC device, use the SoC Builder (SoC Blockset) tool. To generate and execute C code for your SoC models, Embedded Coder® features are required. For more information on generating code for SoC designs, see Generate SoC Design (SoC Blockset).
Embedded Coder does not generate code for this block. In the generated code, the device I/O connects directly to the TCP Write (SoC Blockset), UDP Write (SoC Blockset), or Register Write (SoC Blockset) block.
Introduced in R2020b