DVB-S2X BCH Decoder

R2026b

Decode and recover message from BCH codeword according to DVB-S2X standard

Since R2026b

• 

DVB-S2X BCH Decoder block

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Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The DVB-S2X BCH Decoder block decodes and recovers messages from a Bose-Chaudhuri-Hocquenghem (BCH) codeword according to the Digital Video Broadcasting Satellite Second Generation (DVB-S2X) standard [1]. The block accepts low-density parity-check (LDPC) decoded codeword data bits and a stream of control signals. It outputs decoded message data bits, a stream of control signals, a signal that indicates when the block is ready to accept new input, and an optional signal that provided the number of corrected errors in the output. The block supports either a scalar or an 8-element column vector as input.

The block supports three forward error correction (FEC) frame types, normal, short, and medium. The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in a DVB-S2X receiver for satellite communication.

Examples

New

Decode and Recover Message Using DVB-S2X Standard FEC Decoder

Decode and recover message from codeword using FEC decoder according to DVB-S2X standard.

• Since R2026b
• Open Live Script

Ports

Input

data — Codeword data bits

scalar | column vector

Codeword data bits, specified as a Boolean scalar or an eight-element column vector.

The length of the input data must be based on the FEC frame type and code rate according to the DVB-S2X standard. For more information, see section 5.3 in [1].

For example, if you specify the FEC frame type parameter to Normal and the Code rate parameter to 2/9, the length of the input data must be 14,400.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

frameTypeIdx — Frame type

scalar

Frame type, specified as a scalar.

Specify the frame type as one these options:

• 0— Block considers the input data as a normal frame

• 1— Block considers the input data as a short frame

• 2— Block considers the input data as a medium frame

Dependencies

To enable this port, set the Frame type source parameter to Input port.

Data Types: ufix2

codeRateIdx — Code rate index

scalar

Code rate index, specified as an integer. Code rate index values range from 0 to 34. Each code rate index value represents a specific code rate for each FEC frame type, as shown in this table.

codeRateIdx Value	Code Rate
	Normal	Short	Medium
0	1/4	1/4	1/5
1	1/3	1/3	11/45
2	2/5	2/5	1/3
3	1/2	1/2	NA
4	3/5	3/5
5	2/3	2/3
6	3/4	3/4
7	4/5	4/5
8	5/6	5/6
9	8/9	8/9
10	9/10	11/45
11	2/9	4/15
12	13/45	14/45
13	9/20	7/15
14	90/180	8/15
15	96/180	26/45
16	11/20	32/45
17	100/180	NA
18	104/180
19	26/45
20	18/30
21	28/45
22	23/36
23	116/180
24	20/30
25	124/180
26	25/36
27	128/180
28	13/18
29	132/180
30	22/30
31	135/180
32	140/180
33	7/9
34	154/180

Data Types: ufix6

Output

data — Decoded message bits

scalar | column vector

Decoded message bits, returned as a Boolean scalar or as an eight-element column vector. The output data type and dimension are same as the input.

For more information on extracting output bits for medium frame with vector output, see Extract Output Bits for Medium Frames with Vector Output.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

numCorrErr — Number of corrected errors

scalar

Number of corrected errors, returned as a scalar.

• -1 — Indicates that the block contains errors in its output that cannot be corrected

• 0 — Indicates that the block does not contain errors in its output

• Range from 1 to 12 — Indicates the number of errors corrected in the block output

Dependencies

To enable this port, select the Output number of corrected symbol errors parameter.

Data Types: fixdt(1,5,0)

nextFrame — Block ready indicator

scalar

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

FEC frame source — FEC frame source

Input port (default) | Property

Select the FEC frame source as Property or Input port.

• Property — Select this option to enable the FEC frame type parameter.

• Input port — Select this option to enable the frameTypeIdx port.

FEC frame type — FEC frame type

Normal (default) | Short | Medium

Select the FEC frame type as Normal, Short, or Medium.

For more information about normal, short, and medium FEC frame types, see [1]

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Output number of corrected errors — Number of corrected errors

off (default) | on

Select this parameter to enable the numCorrErr output port. This port outputs the number of corrected errors.

More About

Extract Output Bits for Medium Frames with Vector Output

When you specify an eight-element column vector as input, the DVB-S2X BCH Decoder block outputs decoded BCH message bits as an eight-element vector. For medium FEC frames, the BCH message length, K_BCH, is not a multiple of eight. The supported medium-frame K_BCH values are:

• 5660 bits (code rate 1/5)

• 7740 bits (code rate 11/45)

• 10620 bits (code rate 1/3)

Because these K_BCH values are not multiples of eight, the final output vector of a frame contains four extra bits in addition to the valid BCH output bits. Ignore these extra four bits.

Let k₀, k₁,…, k_BCH-1 denote the BCH-decoded output bits of a medium frame. The block outputs these bits across ceil(KBCH/8) clock cycles according to the following mapping:

Output Element	1st Clock Cycle	2nd Clock Cycle	3rd Clock Cycle	4th Clock Cycle	...	ceil(KBCH/8)-th Clock Cycle
data(0)	k0	k8	k16	k24	...	kBCH-4
data(1)	k1	k9	k17	k25	...	kBCH-3
data(2)	k2	k10	k18	k26	...	kBCH-2
data(3)	k3	k11	k19	k27	...	kBCH-1
data(4)	k4	k12	k20	k28	...	X
data(5)	k5	k13	k21	k29	...	X
data(6)	k6	k14	k22	k30	...	X
data(7)	k7	k15	k23	k31	...	X

In the last output vector, elements represented by X are invalid output bits and must be ignored.

Algorithms

The DVB-S2X BCH Decoder block decodes BCH-encoded codewords by detecting and correcting errors in the received data. For each input frame, the block performs these operations:

• Calculate syndrome values — The block computes syndromes from the received codeword. The syndromes indicate whether errors are present in the input data. This operation occurs during the input phase and does not add additional latency.

• Determine error locator polynomial — The block determines the error location polynomial using the Berlekamp-Massey algorithm. This polynomial identifies the locations of errors in the codeword. For more information about the Berlekamp-Massey algorithm, see Algorithms for BCH and RS Errors-only Decoding.

• Find error locations and error correction — The block evaluates the error locator polynomial using Chien search [2] algorithm to determine the error locations, and correct errors. To improve throughput for DVB-S2X applications, the block evaluates multiple candidates of the error locator polynomial in parallel. When the input data is specified as a vector, the block processes multiple symbols per clock cycle and performs error location detection concurrently across these symbols. This parallel evaluation reduces the number of clock cycles required for error detection compared to scalar processing.

Latency

The latency between valid input data and the corresponding valid output data depends on the input dimension, frame type, code rate, and the number of errors the block can correct. The block determines the latency primarily from the Chien search stage, which evaluates error locations across the BCH codeword. This stage dominates the decoding time because it processes the entire codeword of length NBCH.

For scalar processing, the block performs one operation per cycle and requires approximately NBCH clock cycles.

For vector processing, the block processes multiple samples in parallel and reduces the latency proportionally. For example, when the input vector size is 8, the latency reduces to approximately NBCH/8.

The block can generate output samples while the Chien search is still in progress, which reduces the effective latency compared to designs that wait until the entire decoding operation completes. The latency depends on the selected FEC frame type because the codeword length varies across frame types. Normal frames have the highest latency, followed by medium frames and short frames. The output end signal aligns with the completion of decoding for each input codeword.

This figure shows a Logic Analyzer waveform of the sample output and latency of the DVB-S2X BCH Decoder block for a scalar input when you set the FEC frame type and Code rate values to Normal and 90/180, respectively. The latency of the block is 35,302 cycles.

This figure shows a Logic Analyzer waveform of the sample output and latency of the DVB-S2X BCH Decoder block for a vector input when you set the FEC frame type and Code rate values to Normal and 90/180, respectively. The latency of the block is 6791 cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options.

This table shows the resource and performance data synthesis results for a scalar input and an eight-element column vector input when the FEC frame source is specified as Input port. The generated HDL code is targeted to the AMD^® Zynq^® UltraScale+™ MPSoC - ZCU102 Evaluation Board.

Input Data	Slice LUTs	Slice Registers	DSPs	Block RAMs	Maximum Frequency in MHz
Scalar	12287	8529	0	2	293.88
Vector	15834	10267	0	4	294.77

The maximum throughputs for scalar and vector inputs are 144.36 Mbps and 1045.35 Mbps, respectively. 

References

[1] ETSI Standard EN 302 307-2 V1.1.1: Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications, DVB-S2 Extensions (DVB-S2X),European Telecommunications Standards Institute, Valbonne, France, 2005-03.

[2] Chien, R. “Cyclic Decoding Procedures for Bose- Chaudhuri-Hocquenghem Codes.” IEEE Transactions on Information Theory 10, no. 4 (October 1964): 357–63. https://doi.org/10.1109/TIT.1964.1053699.

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

To obtain effective synthesis results on Intel^® Altera^® devices, perform the following settings:

• For VHDL — In the Configuration Parameters dialog box, go to HDL Code Generation > Global Settings > Coding style tab and set the RAM Architecture parameter to Generic RAM without clock enable.

• For Verilog — In the Configuration Parameters dialog box, go to HDL Code Generation > Global Settings > Coding style tab and clear the Initialize all RAM blocks option.

Restrictions

You cannot generate HDL code for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2026b