HDL OFDM Transmitter

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This example shows how to implement an OFDM-based wireless transmitter in Simulink® that is optimized for HDL code generation and hardware implementation.

This example shows the custom design of an orthogonal frequency-division multiplexing (OFDM) based transmitter. This transmitter model accepts payload data through the input port. It enables you to choose the modulation type and the punctured convolutional code rate of the data from a set of values. These two parameters control the effective data rate of transmission and are provided through the input ports of transmitter. The maximum data rate supported by the transmitter is 3 Mbps. The transmitter also accepts an input valid signal to control the transmission.

The transmitter in this example works in conjunction with the receiver in the HDL OFDM Receiver example. The transmitter has a MATLAB® floating point equivalent function described in the HDL OFDM MATLAB References example.

Transmitter Specification

This section explains the specifications of the transmitter related to the OFDM frame configuration and structure, bandwidth, and sample rate.

The transmitter model accepts two parameters, modTypeIndex and codeRateIndex, which allow you to specify the modulation type and punctured convolutional code rate, respectively, of the data. These two parameters are explained in the following tables:

modTypeIndex

    Value    Represents Modulation Type
    _____    __________________________

      0                BPSK            
      1                QPSK            
      2                16QAM           
      3                64QAM

codeRateIndex

    Value    Represents Code Rate
    _____    ____________________

      0              1/2         
      1              2/3         
      2              3/4         
      3              5/6

OFDM Frame Structure

Every OFDM system has a frame structure that shows the distribution of samples in the frequency domain across all its subcarriers. The frame structure is as shown in the figure. Each OFDM symbol is comprised of 72 subcarriers, and each OFDM frame consists of 36 OFDM symbols. The frame duration is 3 ms. The first OFDM symbol is formed by synchronization sequence (SS), second and third symbols are formed by reference signals (RS), and the fourth symbol is formed by Header. Data is filled from the fifth symbol to the last (36th) symbol. Pilots are inserted between data such that there is one pilot for every five data subcarriers as shown below. These pilots help to detect and correct phase errors at the receiver.

The OFDM parameters used in the model are given below:

           Parameter              Value  
    ________________________    _________

    Sample rate                 1.92 Msps
    Subcarrier spacing          15 kHz   
    FFT Length                  128      
    Bandwidth of OFDM signal    1.4 MHz  
    Active Subcarriers          72       
    Left guard subcarriers      28       
    Right guard subcarriers     27       
    Cyclic Prefix length        32       
    Data symbols per frame      32       
    Pilots per data symbol      12

Model Architecture

The following figure shows the high-level architecture of the OFDM transmitter. There are five different signals that form the OFDM frame: SS, RS, Header, Pilots, and Data. SS, RS, and Pilots are same for every frame. They are stored in separate look up tables (LUT) and accessed whenever required. Header and Data vary based on the inputs given to the transmitter. Header bits are formed based on the input modulation type and code rate values. These header bits are processed through the Header chain as shown in the figure. Payload data is provided as an input to the transmitter. This data is processed through multiple stages in the Data chain. Individual stages in the Header and Data chains are explained in further sections.

These five signals are multiplexed based on their valid signals and stored in a RAM. The RAM holds these signals for a duration of one frame. Data stored in the RAM is read out and modulated by the OFDM Modulator block. The OFDM modulated signal is filtered with a passband frequency of 1.4 MHz and sent out as transmitter output.

File Structure

This example contains two Simulink models, an initialization script, and a MATLAB function:

whdlOFDMTransmitter.slx — This is the top-level model in this example. It has an OFDM Transmitter subsystem that refers to the whdlOFDMTx.slx model. There is an external interface circuit for the OFDM Transmitter subsystem, which provides inputs and collects outputs from the subsystem. Simulating this model runs the remaining three files.

whdlexamples.OFDMTransmitterInit — This script initializes the whdlOFDMTransmitter.slx model. The script is called in the InitFcn callback of the model.

whdlOFDMTx.slx — This model implements the transmitter with total configurability.

whdlexamples.OFDMTxParameters — This function generates parameters required for the whdlOFDMTx.slx model. This function is called in the Model Workspace of the model.

Transmitter Interface

The whdlOFDMTransmitter.slx model shows the OFDM Transmitter subsystem and its interface.

Model Inputs:

modTypeIndex — Selects the type of symbol modulation to be applied to payload data, specified as a ufix2 scalar. This port accepts values 0, 1, 2, and 3, which correspond to modulation types BPSK, QPSK, 16QAM, and 64QAM.

codeRateIndex — Selects the code rate of punctured convolutional code to be applied to payload data, specified as a ufix2 scalar. This port accepts values 0, 1, 2, and 3, which correspond to code rates 1/2, 2/3, 3/4, and 5/6.

data — Input payload data, specified as a Boolean scalar.

valid — Valid signal for the input data, specified as a Boolean scalar.

All input ports run at a sample rate of 30.72 Msps to support different configurations.

Model Outputs:

txData — Transmitter output, returned as a complex scalar with fixdt(1,16,13) datatype sampled at 1.92 Msps.

txValid — Control signal that validates txData, returned as a Boolean scalar sampled at 1.92 Msps.

ready — Control signal that is used to sample input data, modTypeIndex, and codeRateIndex values, specified as a Boolean scalar sampled at 30.72 Msps.

Index Selector

The Index Selector subsystem samples the modTypeIndex and codeRateIndex signals at the rising edge of the ready signal. The subsystem retains the previous outputs if no rising edge exists on the ready signal.

Data and Valid Selector

The Data and Valid Selector subsystem selects the input payload data and input valid signal based on the ready signal.

Structure of the Transmitter

The whdlOFDMTx.slx model is called within the OFDM Transmitter subsystem. It generates an OFDM transmitter waveform by processing input signals in multiple stages as shown below.

whdlOFDMTx

Frame Controller and Input Sampler

The Frame Controller and Input Sampler subsystem generates control signals for later stages of the model. The subsystem also generates a ready output signal that is used for external interfacing. This subsystem samples the input modTypeIndex and codeRateIndex values along with the first valid input sample. The transport block size for the current frame is selected from the Transport Block Size LUT based on the sampled modTypeIndex and codeRateIndex values. The subsystem also generates control signals for header generation followed by the preamble generation along with the first valid sample. Preamble generation refers to the generation of SS, RS, and Pilot signals. The control signal for data generation is asserted either after 9562 (maximum transport block size corresponding to 64-QAM modulation and 5/6 code rate) clock cycles from the first valid sample or after the transport block length of valid input data is stored for the current frame, whichever is later. Along with the data control signal, the ofdmModReady signal is asserted, which indicates the OFDM Modulator block to start modulation.

Frame Generator

The Frame Generator subsystem generates SS, RS, Header, Pilot, and Data signals, which are later OFDM-modulated. The Generate Preamble Control Signals subsystem that is in the Frame Generator subsystem, splits the input preambleSet control signal into ss set, rs set, and pilot set control signals, which generate SS, RS, and Pilot signals, respectively.

Frame Generator/Synchronization Sequence

The Synchronization Sequence subsystem accepts ss set control signal generated from the Frame Controller and Input Sampler subsystem. It is generated considering the length of SS sequence. The counter keeps incrementing and returns SS from an LUT. Once ss set becomes inactive, the counter stops. Output from LUT is upsampled by a factor of 2 to maintain the same sample time as that of the Header and Data subsystems. Reference Signals and Pilot subsystems operate in a similar way by storing the sequences in LUTs and accessing them whenever required.

Frame Generator/Header

The Header subsystem accepts modTypeIndex, codeRateIndex and fftLenIndex as inputs. A headerSet signal starts the header formation. The Header Formation function converts the modTypeIndex and codeRateIndex values into their binary equivalents. For example, a modTypeIndex value of 1 is converted into two bits 01. Similarly, codeRateIndex values are converted into two equivalent bits. To learn more about these indices, refer to Transmitter Specification. fftLenIndex is not configurable and its value is fixed to 0. It is converted to 000, which represents an FFT length of 128. fftLenIndex, modTypeIndex, and codeRateIndex are represented using 3, 2, and 2 bits, forming a total of 7 bits. Additionally, 7 spare bits are added, all currently set to 0, forming a total of 14 Header bits.

These 14 bits are processed as shown in the figure. For proper error detection, General CRC Generator HDL Optimized block pads 16 CRC bits with [16 12 5 0] as the CRC polynomial. The Convolutional Encoder block encodes these 30 bits, that is 14 + 16, with [171 133] as the polynomial and a constraint length as 7. The encoding is processed in terminated mode, adding 6 null bits, that is 7&endash;1, to the CRC padded data. After encoding, these 36 bits result in 72 bits due to the 1/2 rate encoding. The output of the Convolutional Encoder block is a two-element vector that is serialized in the Serialized subsystem using the Serializer1D (HDL Coder) block, leading to rate transition by a factor 2. The serialized data is interleaved using the Interleaver block with 72 as the maximum block size and 18 as the number of columns. For more information on the Interleaver block, see the HDL Interleaver and Deinterleaver example. The interleaved bits are BPSK-modulated using the LTE Symbol Modulator block to form a Header symbol.

Frame Generator/Data

The Data subsystem stores input payload data, dataIn, and processes it through the Data chain.

Frame Generator/Data/Data and Control Signal Generation

The Data and Control Signal Generation subsystem consists of a RAM, where the input payload data, dataIn, is stored. A dataSet signal reads data from this RAM. This subsystem generates start, end, and valid control signals for the RAM data. It also selects the puncture vector based on the codeRateIndex.

Frame Generator/Data/Data Chain

The General CRC Generator HDL Optimized block appends a 32-bit CRC to the payload data from the RAM with [32 26 23 22 16 12 11 10 8 7 5 4 2 1 0] as the CRC polynomial. This CRC-padded data is scrambled with $x^7+x^4+1$ as the polynomial and [1 0 1 1 1 0 1] as the initial state. The Convolutional Encoder block encodes the scrambled data in terminated mode with [171 133] as the polynomial and constraint length as 7. The encoded output is punctured using the Puncturer block with the puncture vector selected in the Data and Control Signal Generation subsystem. The output of the Puncturer block is a two-element vector and is serialized using Serializer1D (HDL Coder) block. The resultant data is interleaved in the Symbol Interleaver subsystem where the Split Data Into Symbols subsystem splits the input data into symbols and each of these symbols are bit-interleaved using the Interleaver block with 360 as the maximum block size and 15 as the number of columns. The supported input data symbol sizes to the Interleaver block are 60, 120, 240, and 360 for BPSK, QPSK, 16-QAM, and 64-QAM modulations, respectively. For more information on the Interleaver block, see the HDL Interleaver and Deinterleaver example. The LTE Symbol Modulator block modulates the interleaved data using the modulation pattern selected based on the input modTypeIndex.

Multiplexer

The Multiplexer subsystem multiplexes the SS, RS, and Pilot signals in the Multiplex Preamble Signals subsystem and the Header and Data signals in the Multiplex Header and Data Signals subsystem based on the valid signals generated by the Frame Generator subsystem.

Frame Formation and OFDM Modulation

The Frame Formation and OFDM Modulation subsystem accepts the preambleData and data signals, and then multiplexes and writes them into a Dual Rate Dual Port RAM (HDL Coder). This RAM reads and writes data at different rates. The RAM writes data at 61.44 Msps. The RAM is filled with data such that it forms an OFDM frame structure as shown in the Transmitter Specification section.

The Generate OFDM Modulator Valid subsystem generates a valid input signal for the OFDM Modulator block at a sample rate of 1.92 Msps and generates a RAM address to read data from the RAM. The valid signal is in synchronization with the ready signal of the OFDM Modulator. The Make OFDM Valid Continuous subsystem selects the OFDM Modulator output based on the validIn signal. It gives out valid OFDM output in the presence of the validIn signal and a dummy OFDM symbol in the absence of validIn signal.

Discrete FIR Filter HDL Optimized

The Discrete FIR Filter HDL Optimized (DSP System Toolbox) block filters the output of the Make OFDM Valid Continuous subsystem with a passband frequency of 1.4 MHz. The whdlexamples.OFDMTxParameters function computes the filter coefficients. The output of the filter is the final output of the transmitter.

Run the Transmitter

The transmitter can be connected back-to-back with the receiver that is explained in the HDL OFDM Receiver example. For more information on how to use the transmitter and receiver Simulink models back-to-back, refer to the HDL OFDM MATLAB References example.

To run the transmitter model, OFDMTxVerification.m script is provided with this example. The script chooses a custom frame configuration, payload data, and simulates the model. The script also collects the simulation outputs and validates them.

NOTE: These files are not available on the MATLAB search path. To copy these files locally to the user path, you must open this example.

Verification and Results

In this section, the OFDM Transmitter Simulink model is validated by comparing its output with its floating point equivalent function, whdlexamples.OFDMTx. For more information on this MATLAB function, see the HDL OFDM MATLAB References example. To compare the output of the Simulink model with the MATLAB function, run the OFDMTxVerification.m script.

>> OFDMTxVerification

### Starting serial model reference simulation build
### Model reference simulation target for whdlOFDMTx is up to date.

Build Summary

0 of 1 models built (1 models already up to date)
Build duration: 0h 0m 2.604s

HDL Code Generation

To generate HDL code for this example, you must have HDL Coder™. Use makehdl and makehdltb commands to generate HDL code and HDL testbench for the OFDM Transmitter subsystem. Testbench generation time depends on the simulation time.

The resulting HDL code is synthesized for the Xilinx® Zynq®-7000 ZC706 evaluation board. The post place and route resource utilization is shown in the table below. The maximum frequency of operation is 230 MHz.

       Resources       Usage
    _______________    _____

    Slice Registers    6373 
    Slice LUT          4197 
    RAMB36             5    
    RAMB18             15   
    DSP48              24