add error plot for this code
i want to add error plot for this code.Can you help?
% Load the engine_dataset
load engine_dataset
% Prepare the data
X = engineInputs.';
Y= engineTargets.';
% Split the data into training and testing sets
cv = cvpartition(size(X,1),'HoldOut',0.2);
Xtrain = X(cv.training,:);
Ytrain = Y(cv.training,:);
Xtest = X(cv.test,:);
Ytest = Y(cv.test,:);
% Train the Gradient Boosting model
Model1 = fitrensemble(Xtrain,Ytrain(:,1),'Method','LSBoost','NumLearningCycles',500,'Learners',templateTree('MaxNumSplits',10));
Model2 = fitrensemble(Xtrain,Ytrain(:,2),'Method','LSBoost','NumLearningCycles',500,'Learners',templateTree('MaxNumSplits',10));
sampleTime = 1;
numSteps = 1199;
time = sampleTime*(0:numSteps-1);
time = time';
simin = timeseries(X,time);
simout = timeseries(Y,time);
model = 'SimMdlName_V1';
system_under_design = [model '/Gradient Boost Predict Model'];
baseline_output = [model '/yarr'];
open_system(model);
hdlsetup(model);
loggingInfo = get_param(model, 'DataLoggingOverride');
sim_out = sim(model, 'SaveFormat', 'Dataset');
plotRegression(sim_out, baseline_output, system_under_design, 'Regression before conversion');
opts = fxpOptimizationOptions();
opts.addTolerance(system_under_design, 1, 'RelTol', 0.05);
opts.addTolerance(system_under_design, 1, 'AbsTol', 50)
opts.AllowableWordLengths = 8:32;
solution = fxpopt(model, system_under_design, opts);
best_solution = solution.explore;
set_param(model, 'DataLoggingOverride', loggingInfo);
Simulink.sdi.markSignalForStreaming([model '/yarr'], 1, 'on');
Simulink.sdi.markSignalForStreaming([model '/diff'], 1, 'on');
sim_out = sim(model, 'SaveFormat', 'Dataset');
plotRegression(sim_out, baseline_output, system_under_design, 'Regression after conversion');
sim_out = sim(model, 'SaveFormat', 'Dataset');
plotRegression(sim_out, baseline_output, system_under_design, 'Regression after function replacement');
systemname = 'SimMdlName_V1/Gradient Boost Predict Model';
workingdir = 'C:/Temp/hdlsrc';
checkhdl(systemname,'TargetDirectory',workingdir,'TargetLanguage','Verilog');
makehdl(systemname,'TargetDirectory',workingdir,'TargetLanguage','Verilog');
makehdltb(systemname,'TargetDirectory',workingdir,'TargetLanguage','Verilog');
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