data synchronization between two control blocks in simulink

I have modelled control algorithm in simulink that takes inputs from ADC. The total design is divided into two blocks, one is ADC block that sends trigger signals to ADC and acquires the data. The other is the control block. The sampling time for control block is 20KHz . I propose to implement these blocks in FPGA with one external clock of 50MHz. Here are my questions:

1. The ADC(external) is a simultaneous sampling ADC, which requires bunch of control signals to acquire data. I need to ensure that data is available to control model, every 50us (20KHz), I do not know how to fix the sampling time requrement for this model (ADC block) in simulink.
2. The code generator in simulink generates verilog code with clock as the input for the model. What is the difference between clock and sampling time? Should I connect this input to 50MHz?
3. Since ADC block is much faster than control block, should I use FIFO or rate transition block to synchronize them. Would it be necessary?
4. Can I just use one clock 50MHz, derive enable signals using counter and control the update rates of these two blocks? If yes how do do it in simulink?