Why does HDL code generation give errors when variable-sized variables are used?

I am trying to generate HDL code for my Simulink model containing a MATLAB function block. My MATLAB function block initializes a persistent variable. The size of the persistent variable is defined using a tunable parameter. When I generate HDL code for my model, I get the following error:

The persistent variable 'variableName' generated for MATLAB Function Block
'modelName/MATLAB Function' has a variable size and is not supported by HDL code generation.
HDL code generation failed for 'MATLAB Function' (#24).

A similar error is observed when I generate HDL code for my MATLAB code containing variable-sized variables:

Variable "variableName" has a variable size and is not supported by HDL code generation.

 Below is sample code that can reproduce the HDL code generation issue :

function y = foo(sizeOfRAM, rdAddr)
 
persistent pRAM;
if isempty(pRAM)
   pRAM = zeros(1, sizeOfRAM);
end
 
y = pRAM(rdAddr);
 
end

I use the following command to generate the HDL code:

>> codegen -config:hdl -args {uint8(0), uint8(0)} foo

Why can't I generate HDL code for variable-sized variables?

Answer 1

[MathWorks Support Team]

Why HDL Coder does not support variable-sizes variables:

HDL code generation does not support variables with variable sizes. In hardware design, memory must have a fixed size because hardware resources are allocated at synthesis time. Variable-sized RAM is not feasible in this context. 

Fixed-size memory is a fundamental requirement in hardware design, especially for HDL code generation. In software, it's common to allocate memory dynamically based on input values or runtime conditions. But in hardware (FPGA/ASIC), memory resources like RAM or FIFO buffers must be sized at design time, not runtime. The primary reasons are as follows:

1. Hardware is static:

• Synthesis of a chip creates a physical layout of logic gates, flip-flops, and memory blocks.
• All resources must be explicitly defined; there is no provision for "input dependent" resources.
• Defining RAM size based on an input pin is not possible, as the synthesis tool cannot determine how much memory to allocate without fixed specifications.
• Once fabricated, the physical layout of a chip cannot change depending on input values.

2. Input pins are runtime signals:

• Input pins are evaluated after the chip is built and deployed. These pins can control behavior (such as read/write operations), but cannot define structural aspects like memory size.

3. RAM blocks are predefined:

• FPGAs and ASICs utilize memory blocks with fixed sizes (e.g., 512x8, 1024x16).
• Multiple blocks can be instantiated or configured, but the configuration must be decided before synthesis.

4. Variable size and addressing logic:

• Variable RAM size will require variable address width.
• This will affect all related logic (e.g., counters, address decoders) potentially making the design unsynthesizable.

Summary:

For HDL code generation, the structure of the design is fixed at synthesis time, while behavior can be flexible at runtime. Defining RAM size via input pins violates this principle, which is why HDL Coder throws an error when variable-sized variables are detected.

Try This Workaround:

To address errors related to variable size in HDL code generation, please ensure the following:

• All variables have a predefined size, using a constant or parameter.
• If a parameter is used to define the size of any variable, then that parameter should be set as non-tunable.
• For a MATLAB function block, uncheck "Support variable-size arrays" from the Advanced properties section. This will detect variable sizes when the model is updated or simulated.

Please refer to the examples below, demonstrating the use of RAM. The examples can be accessed by running the following code:

>> mlhdlc_demo_setup('ram') % basic RAM examples
>> mlhdlc_demo_setup(heq') % use of RAM in an image processing algorithm

Further details on some of the examples obtained using above commands are available at the following documentation pages:

MAP Matrices to Block RAMs to reduce Area

HDL Code Generation from hdl.RAM System Object

Image Enhancement by Histogram Equalization