Problem with Generating VHDL Code of a Subsystem based on "Bus Creator", using HDL Coder 3.0

Hi everyone.

I'm trying generating VHDL code of a subsystem using the HDL Coder 3.0, you can see the subsystem doing click on link bellow

http://img717.imageshack.us/img717/8330/hdlgenerating.png

when I use the "Check Subsystem Compatibility", appear a report with error , click on link below to see.

http://img256.imageshack.us/img256/2501/messageerrorhdlcompatib.png

I attached the files of simulink and buses:

http://sourceforge.net/projects/simustruct/files/files%20simulink.rar/download

I thought HDL Coder v3 supported the Bus Creator. I hope You can help me.

Answer 1

[Tim McBrayer]

It appears that HDL Coder does not support nested busses, and is not reporting this gracefully to the user. I replaced your 2x9 nested bus with a flat, 18-element bus, and HDL Coder successfully emitted the correct code. Thank you for bringing this issue to our attention.