Generating HDL code for look up table

Hello everyone, I have generated a HDL code(Verilog to be specific) using MATLAB 1D look-up table. The problem I have is that when I input an array into the table, the code creates multiple look-up table depending on the number of arrays which makes the code extremely inefficient. For example let's assume the look up table up table describes the cosine function and the number of colomns are 360. In this case I am inputting an array to the look up table which are shifted 90 degree with respect to each other. Basically when the first element of the array is 0 the second is 90 , when its 1 the second is 91 and so on. the problem is that the generated code creates a different look up table for the second element of the array rather than using the same look up table used for the first element of array.Therefore rather than ending up with 360 saved values, it ends up with 720 saved values which consumes double the amount of space. So in short is it possible to generate a HDL code for look up table, which only generates 1 look-up table for an input array. I appreciate any help.

Regards, Kamyar

Answer 1

[Tim McBrayer]

The short answer is no, HDL Coder cannot do this. This is because you are asking for hardware to look up two values at the same time. Since a ROM implementation on an FPGA has a single read port, the two reads must be serialized either in time or in space. HDL Coder is choosing space, in this case.

If space is a a premium, you need to feed your two array values sequentially to the lookup table. Then you'll get a single table, probably running at twice the clock rate, in order to deliver the two outputs within a single clock cycle.

[Kamyar Khosravi]

Hi Tim,

Thank you for the quick response. I believe I totally understood your explanation.