Problem in conversion from model to VHDL/Verilog HDL

Dear all

Recently, I built up a model by basic blocks and stateflow in hdllib.Functional simulation results of floating point model and fixed point model were both acceptable. Then, verilog hdl code files were generated. However, the simulation result in modelsim was not satisfied. Timing problem occured.

I think the problem is the operations such as multiply and add have zero delay in simulink. However, each operation spends time in actual. I used to implement design by using system generator. Latency in any basic block such as multiplier and adder in System generator is user-defined. Besides, it help users analyze timing problem.

Can anybody tell how to cosider the timing problem when we build up model in simulink? Can you trust HDL coder?

Answer 1

[Tim McBrayer]

HDL Coder will faithfully translate your Simulink design into VHDL or Verilog. The resulting HDL code is bit-true and cycle-accurate. If you do not model any timing (that is, no registers, so the design is purely combinatorial), no clocking will be generated and your design will propagate its results with zero delay. HDL Coder's generated HDL testbench will exercise the generated HDL code for the DUT in same fashion as Simulink, with the identical data at analogous times. With HDL Verifier you can even cosimulate your generated HDL design inside Simulation for additional verification.

HDL Coder does not model any sort of explicit time delays in the generated HDL code because that information is not part of the Simulink design. The tool has no way of knowing how long (in real time) e.g. a hardware multiply might take, because the target hardware could be anything from the smallest FPGA to a custom ASIC. Again, the generated code is clock cycle accurate.

What you might want to do is model delays in your Simulink model. These will show up as registers in your HDL code. This can be done in several different ways. You can model them explicitly, using the Delay block. You can add input or output pipelining to any block or subsystem via the HDL Block Properties right-click menu. You can enable Distributed Pipelining for a subsystem so that any available delays will be propagated throughout the generated logic to balance the pipelining and improve the overall speed of the synthesized results. You can constrain registers as well, to require them to appear at specific locations in your design, if so desired.

[Bo]

Dear Tim McBrayer, thanks for your quickly replying.

What I wanna do is considering timing problem in FPGA when I build system model by using basic model. My desin contain too many feedbacks. Timing requirement for closed loop system is very strict. I have to modify the generated hdl code myself if the products of mathworks cannot help me solve timing problems. Workload is very large.

It is a simple example, a+a*a=b. a and a*a should be provided for add operation at the same time. However,it is zero delay in multiply operation in simulink(all the modes are hdlsupported). Can you show me how to keep the behavior of generated hdl code be the same as simulink model?