Problem of reciprocal building block in hdl code generation

Dear all,

I used a periodic signal (Ts is period) as the input signal of the reciprocal of square root building block in simulink but the experiment result indicated the period of the output signal of the reciprocalof square root building block was 3*Ts. Did anybody know how to resolve this problem?

[TAB]

Square root building block can not change the period of input signal.

Can you clarify what are you doing and what you expect ?

Also which source block you are using ?

[Bo]

Dear TAB, please read the answer from Tim McBrayer. His words indicated he know the problem I faced. The problem is introduced by reciprocal of square root building block.

Answer 1

[Tim McBrayer]

The Reciprocal Sqrt Block implementation supports calculation using unsigned, fixed-point data types. It uses the iterative Newton-Raphson approximation algorithm, using three iterations by default. (The number of iterations desired is settable on the block mask, trading off speed for accuracy.) Each iteration requires a clock cycle to compute.

In order to match Simulink's results, the iteration stages of the Sqrt implementation require the clock to be 3x faster than the data rate. The implementation also requires latency for the initial results to be generated. These are both noted in the on-screen output of HDL Coder.

Here is the relevant the output from a DUT containing a single, 3-iteration Reciprocal Sqrt block:

 ### 'The code generation and optimization options you have chosen have introduced additional pipeline delays.
The delay balancing feature has automatically inserted matching delays for compensation.'
 ### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
 ### Output port 0: 5 cycles.
 ### Begin VHDL Code Generation for 'untitled'.
 ### MESSAGE: The design requires 3 times faster clock with respect to the base rate = 1.

The last line indicates that the design requires a clock 3x faster than the Simulink base rate. Since the inputs and outputs run at the Simulink base rate, this implies the hardware clock must be 3x faster than the input data and the output sampling rate. The output also informs the user that the implementation has a 5-cycle latency on the block's output, required for the calculation pipeline to fill with data. Once the pipeline is full new results are generated at the input data rate.

More information on how and why overclocking is necessary may be found in the product documentation.

[Bo]

Dear Tim McBrayer, your answer is correct. Yesterday, I planed to isolate the reciprocal of square root building block but I failed. Do you have any good method?

[Tim McBrayer]

I'm not sure what you're asking here. In my example I simply had one block in it: Simulink/Math Operations/Reciprocal Sqrt. I am not sure what you mean by 'isolate' in your comment.

[Bo]

Dear Tim McBrayer. Finally, I built up Newton-Raphson approximation algorithm myself and the experiment result in FPGA is excellent. Thanks all the same.