Rate transition problem using upsample,repeat or rate transition block for generating HDL code

Dear all,

I wanna change the rate of a signal from slow stepsize to fast stepsize. For instance, there is a sine signal. Its sample period is 0.0001s. I'd like to change the rate from 0.0001s to 0.000025s under fixed-step case. I found upsample block, repeat block and rate transition block would introduce 0.0001s delay. 0.0001s delay would disppear if I used upsample block or repeat block under variable-step. I have ever used upsample block provided by system generator, and I can select 0 delay.

Does anybody know how to change the rate using blocks provided by mathworks without 0.0001s delay under fixed-step?