Using MATLAB and FPGA-in-the-Loop to design a filter.

versión 1.0 (2.65 MB) por Pablo Trujillo Juan
Workflow to design, test, verify and implement a filter on FPGA.

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Actualizada 20 Dec 2020

De GitHub

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This project describes the entire workflow to design a filter and implement it on an FPGA.
- Study the filter requirements.
- Design the filter using Filter Designer tool.
- Test the filter, and the quantified filter on MATLAB and Simulink.
- Generate the HDL code of the filter.
- Verify the filter on the corresponding device using FPGA-in-the-Loop
- Integrate the filter on a Vivado design and test it on the application.

Citar como

Pablo Trujillo Juan (2022). Using MATLAB and FPGA-in-the-Loop to design a filter. (https://github.com/controlpaths/line_filtering/releases/tag/1.0), GitHub. Recuperado .

Compatibilidad con la versión de MATLAB
Se creó con R2020b
Compatible con cualquier versión
Compatibilidad con las plataformas
Windows macOS Linux

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Para consultar o informar de algún problema sobre este complemento de GitHub, visite el repositorio de GitHub.
Para consultar o informar de algún problema sobre este complemento de GitHub, visite el repositorio de GitHub.