Using MATLAB and FPGA-in-the-Loop to design a filter.
Updated 20 Dec 2020
This project describes the entire workflow to design a filter and implement it on an FPGA.
- Study the filter requirements.
- Design the filter using Filter Designer tool.
- Test the filter, and the quantified filter on MATLAB and Simulink.
- Generate the HDL code of the filter.
- Verify the filter on the corresponding device using FPGA-in-the-Loop
- Integrate the filter on a Vivado design and test it on the application.
Pablo Trujillo Juan (2021). Using MATLAB and FPGA-in-the-Loop to design a filter. (https://github.com/controlpaths/line_filtering/releases/tag/1.0), GitHub. Retrieved .
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