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HDL Coder with Xilinx Sysgen R2013b
Using Xilinx® System Generator for DSP with HDL Coder™ This example shows how to use Xilinx System Generator for DSP with HDL C...

alrededor de 5 años hace | 0

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Hi sir i am working on hdl coder and i am new to it and my pbm is have written the matlab code and compiled it sucessfully, even generated hdl code but in hdl test bench i am not getting the exact ans( matlab output and hdl output not matching).
HDL Coder generates bit true and cycle accurate code corresponding to the design. The testbench captures the stimulus and respon...

alrededor de 5 años hace | 0

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sir I want to convert my .m file to VHDL . my code is given below.
You need to break the design into two parts. A testbench and a design. Follow basic example shown here. >> mlhdlc_demo_setup('...

alrededor de 5 años hace | 0

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How to do area optimization(sharing and streaming) with feedback loop like that AGC or AFC in communication system?
To address pipelining of blocks in feedback loops you can refer to this example and related HDL Coder features. https://www.mat...

alrededor de 5 años hace | 0

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I want to generate hdl code using Matlab simulink. But getting a error, I have attached my Matlab Code. please help
You have to break the script into design and testbench. See basic examples in the documentation. >> mlhdlc_demo_setup('sfir') ...

alrededor de 5 años hace | 0

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Suggest a good reference book for Simulink and/or MATLAB to HDL Code converter
HDL Code Generation from MATLAB Generate HDL Code from MATLAB® algorithms Implement your MATLAB algorithm in hardware by gen...

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how can i solve the message below?
see example usage in HDL Code Generation from System Objects

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ROM block generated by HDL Coder not inferred by Vivado Synthesis tool
It is possible LUT size in your model does not meet the threshold for ROM mapping on the synthesis tool. Try the example belo...

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How do I convert matlab code to VHDL in matlab 15?
Try basic MATLAB to HDL examples. mlhdlc_demo_setup('sfir') mlhdlc_demo_setup('heq')

alrededor de 5 años hace | 0

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HDL Coder generates VHD Files for Sample and Hold Blocks
Attached model has several Sample and Hold Blocks in addition to Sin function configured to use CORDIC architecture. The fla...

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Interfacing an FPGA to an SRAM which has a bidirectional data bus
Specify Bidirectional Ports https://www.mathworks.com/help/hdlcoder/ug/specify-bidirectional-ports.html#buaztj8 You cannot s...

alrededor de 5 años hace | 0

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HDL Coder, Assigning specific pins to IO signals for a custom FPGA
https://www.mathworks.com/help/hdlcoder/ug/save-target-hardware-settings-in-model.html You need to Set Target > Set Target In...

alrededor de 5 años hace | 0

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Timing constraints file for hdl coder
In MATLAB to HDL GUI project you can include additional project files related to constraints. Add these two files in the lo...

alrededor de 5 años hace | 1

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Need help regarding matlab code implementation on FPGA
Follow instructions here Demo Basic HDL Code Generation and FPGA Synthesis from MATLAB Documentation HDL Code Generation from ...

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Does anyone could give me a hint about using the dsp.HDLIFFT in my code for HDL Code Generation?
MATLAB Design function [yOut,validOut] = HDLFFT128(yIn,validIn) persistent fft128; if isempty(fft128) fft128 = dsp.HDLFF...

alrededor de 5 años hace | 0

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HDL Coder creates too many files in my full model, but works as expected on a subystem
Sharing requirements for generating reusable code from atomic and virtual subsystems in Simulink models from R2021a documentatio...

alrededor de 5 años hace | 0

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Why am I getting inconsistent data from my HDL Coder implementation?
Please reach out to support@mathworks.com with reproduction steps.

alrededor de 5 años hace | 0

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System object methods can only be called once
Consider splitting the logic into reset, update, output secttions. Persistent variables result in registers. Persistent variabl...

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Settings for fixed clock naming in Simple Dual Port RAM generation?
It looks like you are using 'ClockInputs', 'Multiple' option in HDL Coder that leads to generation of logic with Multiple Clocks...

alrededor de 5 años hace | 0

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HDL workflow adviser error, oversampling error!?
Your MATLAB code is using floating-point double precision. You need to have budget for pipelining for math in the logic. Consi...

alrededor de 5 años hace | 1

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HDL workflow adviser error, oversampling error!?
What release are you using? Can you share a sample model that can reproduce the issue? >> makehdl(gcb) ### Generating ...

alrededor de 5 años hace | 0

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IO blocks aren't created when using HDL coder based on Simulink models, but they are when the code is based on MATLAB scripts
Attached Sample MATLAB code and Simulink model for a simple wire and their generated identical code. Can you share the model /...

alrededor de 5 años hace | 0

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Pulse Generator For HDL conversion!
>> When i try to generate code, HDL Coder says that the pulse generator isn't supported for HDL ! You can build pulse ge...

alrededor de 5 años hace | 0

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Testbench for floating point model-hdl coder
You can use the HDL Coder toolstrip or configset to generate code and testbench from the UI. HDL Coder generates code for the d...

alrededor de 5 años hace | 0

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Testbench for floating point model-hdl coder
you can try one of the basic example models with floating point and try to generte code and testbench. check documentation for...

alrededor de 5 años hace | 0

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System Generator: HDL Black Box include mem files.
It looks like it is being addressed here. https://forums.xilinx.com/t5/AI-Engine-DSP-IP-and-Tools/System-Generator-HDL-Black-B...

alrededor de 5 años hace | 0

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Simulink HDL Coder D-FF With Trigger that isn't clock
you can generate negative edge reset using ResetAssertedLevel option makehdl(gcb, 'triggerasclock', 'on' , 'ResetAssertedLevel'...

alrededor de 5 años hace | 1

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Simulink HDL Coder D-FF With Trigger that isn't clock
The requirement is relaxed in the newer releases. makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on'...

alrededor de 5 años hace | 1

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HDL Advisor Crashing on startup; Error using sdi.Repository/getProperty
This is issue is not reproducible. >> hdladvisor('hdlcoder_sfir_fixed_stream/DUT') Updating Model Advisor cache... Model ...

alrededor de 5 años hace | 0

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warnings in hdl code generation
Begin with one of the predefined HDL templates to avoid such warnings. % Simulink >> create new model >> and select HDL Cod...

alrededor de 5 años hace | 0