Respondida
Error - periodic sample time - Pixels to Frame
The pixelIn and controlIn should be operating at the same rate when using pixel streaming based interface. https://www.mathwo...

alrededor de 3 años hace | 0

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HDL Workflow Adviser Error: Abnormal exit: Invalid Simulink object name: stateflow
This error is unrelated to the name of the chart. Probably a corrupt model or an internal issue during HDL Code generation. If...

alrededor de 3 años hace | 0

Respondida
HDL Code Generation Check Report - word width error
You have to constrain the operator wordlength to be within 128 bit limit for HDL Code generation.

alrededor de 3 años hace | 0

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How to use proprietary IPS with HDL coder?
When generating RTL from Simulink model or MATLAB algorithm, there are several ways to integrate custom HDL IP with HDL Coder ge...

alrededor de 3 años hace | 0

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design and implement adaptive filter for noise signals cancellation in ecg and heartbeat
https://www.mathworks.com/matlabcentral/fileexchange/35328-simulink-model-for-fetal-ecg-extraction-hdl-compatible-algorithm

alrededor de 3 años hace | 0

Respondida
Error Cannot find a valid sample time for the model. Continuous signal rates are not supported in native floating-point mode.
This is error is auto-resolved in HDL Coder starting R2023a release. https://www.mathworks.com/help/hdlcoder/release-notes.htm...

alrededor de 3 años hace | 1

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Error in converting function into fixed point using HDL Coder
Getting Started with Targeting Xilinx Zynq Platform This example shows how to use the hardware-software co-design workflow to b...

alrededor de 3 años hace | 0

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Is there any plan to support Vivado ML for the HDL Coder tools?
Vivado ML Editions is the FPGA EDA tool suite from AMD/Xilinx based on machine-learning optimization algorithms, as well as ad...

alrededor de 3 años hace | 0

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Example HDL QAM : changing QAM 64 to QAM 256
It looks like you are stuck modifying the existing to QAM 256. Please reach out to tech support for additional guidance. They ca...

alrededor de 3 años hace | 0

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Can I use HDL Coder without a Vivado license in my machine?
HDL Coder generates synthesizable VHDL and Verilog code. You can use the target settings to customize the code for a specific ha...

alrededor de 3 años hace | 0

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Respondida
What are MIL, SIL, PIL, and HIL, and how do they integrate with the Model-Based Design approach?
“M”, “S”, “P” and “H” are all referring to the Controller. PIL uses the Controller Processor only (no I/O connectivity), HIL ...

alrededor de 3 años hace | 2

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Error: variable-size matrix type is not supported for HDL code
Variable dimensions are not synthesizable to hardware and hence not supported for HDL Code generation. >> mlhdlc_demo_setup...

alrededor de 3 años hace | 0

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import hdl coder fails, why?
This is a limitaiton of importhdl feature. In general only subset of verilog is convertible to Simulink using this feature.

alrededor de 3 años hace | 0

Respondida
When using Simulink External Mode with an AXI4-Stream IIO Read block, if the timeout value is greater than zero, it cause the simulation time to be slower than actual time
The timeout behavior is expected, the timeout leads to overrun in the software task and so the time step will get out of sync wi...

más de 3 años hace | 0

Respondida
Issue in HDL Coder
t = 1:10; x = [4 8 6 -1 -2 -3 -1 3 4 5]; yc = movmean(x,5); plot(t,x,t,yc); The movemean fun...

más de 3 años hace | 0

Respondida
Issue in HDL Coder
Can you share the design, testbench and project files? Feel free to reach out to MathWorks tech support or DM me with the repro...

más de 3 años hace | 0

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Errors : algebraic loop in use HDL simulink coder
https://www.mathworks.com/matlabcentral/answers/95310-what-are-algebraic-loops-in-simulink-and-how-do-i-solve-them Models with ...

más de 3 años hace | 0

Respondida
error HDL compilation failed
Can you check if all the design files are added to the filWizard? There seems to be a pilot error and some package files are mis...

más de 3 años hace | 0

Respondida
select MIcrochip Libero as target and get error saying "Index exceeds the number of array elements. Index must not exceed 0."
https://www.mathworks.com/support/bugreports/2772641 This is a known issue addressed in the R2022b Update3 and the recent R20...

más de 3 años hace | 1

Respondida
Assertion failed: b:\matlab\src\cgir_hdl\target_analysis\characterizationkeygenerator.cpp:45:val
https://www.mathworks.com/help/hdlcoder/ug/find-estimated-critical-paths-without-synthesis-tools.html Critical Path Estimation ...

más de 3 años hace | 0

Respondida
MATLAB compatibility with VIVADO 2018.2 and VIVADO 2019.2
https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-c...

más de 3 años hace | 0

Respondida
Error Goto/From connections subsystem boundaries
https://www.mathworks.com/help/hdlcoder/ug/deploy-buck-converter-to-speedgoat-io-modules-workflow-script.html Deploy Simscape...

más de 3 años hace | 0

Respondida
Unsupported dimensions of matrix type at output port 0
Matrices are supported at the DUT boundary in HDL Coder https://www.mathworks.com/help/hdlcoder/io-optimization.html?s_tid=CRUX...

más de 3 años hace | 0

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Introduce Zybo board in Simulink HDL coder workflow advisor
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html This ex...

más de 3 años hace | 0

Respondida
I am having a problem in converting matlab to vhdl code
Consider reviewing the example below for best practices for MATLAB to HDL code generation. >> mlhdlc_demo_setup('mlhdlc_fft_cha...

más de 3 años hace | 0

Respondida
xilinx blockset is not shown in simulink library
https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html Vitis Model Composer by: Xilinx, Inc Vitis™ Mode...

más de 3 años hace | 0

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Simulink models to Verilog HDL coder
Matrix IO is now supported with HDL Coder https://www.mathworks.com/help/hdlcoder/io-optimization.html?s_tid=CRUX_topnav htt...

más de 3 años hace | 0

Respondida
Xilinx Zynq ZCU104 evaluation board support
Customizing HDL Coder workflow for ZCU104 board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-an...

más de 3 años hace | 0

Respondida
SoC Builder fails to deploy on Xilinx ZCU104 FPGA Board
HDL Coder workflow to add a custom ZCU104 board https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and...

más de 3 años hace | 0

Respondida
Adding Xilinx ZCU104 board to SoC Blockset
Customizing the HDL Coder workflow for ZCU104 board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-boar...

más de 3 años hace | 0