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HDL Code Generation

Generate HDL code from MATLAB® and Simulink®

To implement a DSP design on FPGAs or ASICs, you can use either HDL Coder™ or Filter Design HDL Coder™. Both products generate synthesizable and portable VHDL® and Verilog® code, and also generate VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code.

  • HDL Coder — Generate code from Simulink or MATLAB designs. Supported blocks in DSP System Toolbox™ and DSP HDL Toolbox include filters, math and signal operations, and other algorithms optimized for resource use and performance, such as the FFT (DSP HDL Toolbox), Discrete FIR Filter (DSP HDL Toolbox), and NCO (DSP HDL Toolbox) blocks. For a basic example of how to generate HDL code using HDL Coder, see Programmable FIR Filter for FPGA. For an introduction to DSP HDL Toolbox™, see Implement FFT Algorithm for FPGA (DSP HDL Toolbox).

  • Filter Design HDL Coder — Generate code from MATLAB filter designs. You can access code and test bench generation features using the Generate HDL user interface, or by using command-line options. These features are also integrated with the Filter Designer app. For an example of how to generate HDL code using Filter Design HDL Coder, see HDL Butterworth Filter (Filter Design HDL Coder).

To debug your designs in Simulink or MATLAB, use the Logic Analyzer waveform viewer.

Simulink Visualization Tool

Logic AnalyzerVisualize, measure, and analyze transitions and states over time


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