When you generate HDL code, you can optionally generate a Simulink model that includes an HDL Cosimulation block that runs your generated HDL code in an HDL simulator. The model also includes your original Simulink stimulus generation, behavioral model, and blocks that display or analyze output. The model compares the output of the HDL Cosimulation block against the output of the source subsystem.
|Generate HDL test bench from model or subsystem|
Test Bench Generation Output and Postfix
- HDL Cosimulation (HDL Verifier)
The HDL Verifier software consists of MATLAB® functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
- Generate a Cosimulation Model
Automatically generate a Simulink model that cosimulates with your HDL simulator.
- Set Up for HDL Cosimulation (HDL Verifier)
To cosimulate your HDL code with a MATLAB or Simulink design, you must first:
- Automatic Verification of Generated HDL Code from Simulink (HDL Verifier)
Verify generated HDL code using a generated cosimulation model.
- Choose a Test Bench for Generated HDL Code
Select a generated test bench.