Verification and Debugging
R2026bSimulate and verify generated HDL code
When you generate HDL code, you can optionally generate a test bench that verifies your generated HDL code against your Simulink model. You can verify the generated code by using HDL test bench. For more information on choosing the type of test bench to generate, see Choose a Test Bench for Generated HDL Code.
Categories
- HDL Test Bench Generation
Generate a test bench that verifies generated HDL code against test vectors from MATLAB® or Simulink®
- Cosimulation
Run generated HDL code in HDL simulator
- SystemVerilog DPI Test Bench
Generate DPI test bench code from entire Simulink model
- FPGA-in-the-Loop Simulation
Verification with FPGA hardware
- FPGA Data Capture
Capture signal data from live FPGA
- AXI Manager
Access AXI subordinate memory on FPGA board from MATLAB or Simulink
Featured Examples
HDL Verifier Cosimulation Model Generation in HDL Coder
Reuse an existing Simulink® model to verify HDL Coder™ generated hardware designs using an HDL Verifier™ cosimulation test bench.
Debug IP Core Using FPGA Data Capture
Debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together. This example also shows how to capture a large amount of data to external memory using FPGA Data Capture.
