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Speed and Area Optimization

Improvements through resource sharing, streaming, pipelining, RAM mapping, loop optimization

For your target hardware, generate HDL code from a Simulink® model that meets timing and area requirements by using speed and area optimizations. Area optimizations reduce resource usage of your design. Speed optimizations improve the timing of your design on the target FPGA so that your design runs at higher frequencies by optimizing the critical path. To learn more about each type of optimization in HDL Coder™, see Speed and Area Optimizations in HDL Coder.


  • Optimization Basics
    Hierarchy flattening, delay balancing, validation model, constrained overclocking, and feedback loop highlighting
  • Area Optimization
    RAM mapping, resource sharing, and streaming
  • Speed Optimization
    Critical path estimation and reduction, pipeline register insertion, loop unrolling, and automated iterative clock frequency optimization
  • I/O Optimization
    I/O improvements using frame-to-sample conversion, multiple sampling handling, and I/O thresholding