Native Floating Point
R2026bHDL Coder™ native floating-point technology can generate HDL code from your floating-point design. These are some of the key features:
Generation of target-independent HDL code that you can deploy on any FPGA or ASIC.
Support for the full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes.
Extensive support for math and trigonometric blocks.
Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.
Classes
hdlcoder.FloatingPointTargetConfig | Floating-point target configuration for floating-point library |
hdlcoder.FloatingPointTargetConfig.IPConfig | IP settings for selected floating-point configuration |
Functions
createFloatingPointTargetConfig | Create floating-point target configuration for floating-point library that you specify |
Blocks
 | Float Typecast | Typecast data between unsigned integers and floating-point data types |
Model Settings
Checks
Topics
Native Floating-Point Fundamentals
- Getting Started with HDL Coder Native Floating-Point Support
Learn about the native floating point support in HDL Coder. - Native Floating Point Support for Simulink Blocks
List of operators and supported blocks in the floating-point model. - Numeric Considerations for Native Floating-Point
Learn about nearest even-digit rounding, denormal numbers, exception handling, and relative accuracy and ULP considerations. - ULP Considerations of Native Floating-Point Operators
ULP considerations, ULP values of native floating-point operators, and adherence to IEEE-754 compliance. - Latency Considerations with Native Floating Point
Learn how to view the latency of a floating point operator and the various ways to customize it. - Latency Values of Floating-Point Operators
Latency values of operations supported in native floating-point mode.
Code Generation with Native Floating-Point
- Generate Target-Independent HDL Code with Native Floating-Point
Generate HDL code from floating-point Simulink® models. - Verify the Generated Code from Native Floating-Point
How you can verify the generated code from the floating-point model using HDL Testbench, Cosimulation, and FPGA-in-the-loop. - Synthesis Benchmark of Common Native Floating Point Operators
This example shows how to access and generate synthesis benchmarks for common native floating-point operators with Xilinx® Vivado® and Intel® Quartus® tool.
HDL Block Properties
- HDL Block Properties: Native Floating Point
HDL code generation parameters for native floating-point block implementations.
Related Information
Troubleshooting
Optimize Generated HDL Code for Multirate Designs with Large Rate Differentials
Causes and possible solutions for fixing HDL code generation issues with multirate models that have large rate differentials.
Featured Examples
Floating Point Support: Field-Oriented Control Algorithm
In this example you review a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM) implemented using single-precision and half-precision floating-point types.
Optimize Feedback Loop Design and Maintain High Data Precision for HDL Code Generation
Optimize a feedback loop design and maintain high data precision for HDL code generation by using native floating point and clock-rate pipelining when generating HDL code from a MATLAB® design.
Generate HDL Code from MATLAB Code by Using Native Floating-Point and Vendor Floating-Point Library IP
Generate HDL code from MATLAB® code by using HDL Coder™ native floating-point (NFP) and vendor floating-point library IP. In this example, you use AMD® floating-point from the AMD® Vivado synthesis tool together with HDL Coder native floating-point in the same generated design.
