hdlcoder.FloatingPointTargetConfig Class
Namespace: hdlcoder
Floating-point target configuration for floating-point library
Description
Use objects of the hdlcoder.FloatingPointTargetConfig class to configure
the floating-point target for a floating-point library. You can create either a native
floating-point configuration object or a mixed native floating-point and vendor-specific
floating point target configuration object for these vendor-specific floating-point libraries:
Altera® Megafunctions (ALTERA FP Functions)
Altera Megafunctions (ALTFP)
Xilinx® LogiCORE®
AMD® Floating-Point Operators
Creation
Create an hdlcoder.FloatingPointTargetConfig object by using the createFloatingPointTargetConfig method.
Properties
VendorFloatingPointLibrary — Vendor-specific floating-point library name
"None" (default) | "ALTERAFPFUNCTIONS" | "ALTFP" | "XILINXLOGICORE" | "AMDFloatingPointOperators"
Vendor-specific floating-point library name, specified as "None",
"ALTERAFPFUNCTIONS", "ALTFP",
"XILINXLOGICORE" or "AMDFloatingPointOperators".
Specify the vendor-specific library to use in combination with the native floating-point
(NFP) library.
To set properties of the vendor-specific floating-point library, use the hdlcoder.FloatingPointTargetConfig object.
Example: "ALTFP"
Data Types: char | string
HandleDenormals — Specify whether to handle denormal numbers in your design
"Auto" (default) | "on" | "off"
Specify whether you want HDL Coder™ to handle denormal numbers in your design. Specify this property as a string array or character vector. Denormal numbers are nonzero numbers that are less than the smallest normal number.
Data Types: char | string
LatencyStrategy — Specify whether to use maximum or minimum latency for the native floating-point operator
"MAX" (default) | "MIN" | 'ZERO'
Specify whether you want HDL Coder to use a maximum or a minimum latency setting for the floating-operators that your design uses. Specify this property as a string array or character vector.
Data Types: char | string
MantissaMultiplyStrategy — Specify how you want HDL Coder to implement the mantissa multiplication operation when your design uses floating-point multipliers
"FullMultiplier" (default) | "PartMultiplierPartAddShift" | "NoMultiplierFullAddShift"
Specify how you want HDL Coder to implement the mantissa multiplication process for floating-point multipliers in your design. You can control the Digital Signal Processor (DSP) use on the target platform for your design. To learn more, see Mantissa Multiplier Strategy.
Data Types: char | string
InitializeIPPipelinesToZero — Whether to initialize pipeline registers in Altera Megafunction IP to zero
true (default) | false
Whether to initialize the pipeline registers in the Altera Megafunction IP to zero, specified as a logical. To
avoid potential numeric mismatches in the HDL simulation, set
InitializeIPPipelinesToZero to true. To
specify this property, set VendorFloatingPointLibrary to
"ALTERAFPFUNCTIONS".
Data Types: logical
LatencyStrategy — Whether to use maximum or minimum latency
"MIN" (default) | "MAX"
Whether to use minimum or a maximum latency when mapping your design to FPGA
floating-point target libraries, specified as "MIN" or
"MAX". To specify this property, set
VendorFloatingPointLibrary to "ALTFP",
"XILINXLOGICORE" or
"AMDFloatingPointOperators".
Data Types: char | string
Objective — Whether to optimize design for speed or area
"SPEED" (default) | "AREA"
Whether you want to optimize the design for speed or area when mapping your design
to FPGA floating-point target libraries, specified as "SPEED" or
"AREA". To specify this property, set
VendorFloatingPointLibrary to "ALTFP",
"XILINXLOGICORE" or
"AMDFloatingPointOperators".
Data Types: char | string
DSPSliceUsage — Choose DSP mode to map FPGA floating-point library
"Primitive" (default) | "Full"
Choose DSP usage mode to map your design with AMD floating-point IPs on FPGA,
specified as "Full" or "Primitive". To specify
this property, set VendorFloatingPointLibrary to
"AMDFloatingPointOperators".
For Versal® devices, floating-point operators such as multipliers and adders are mapped to DSPFP32 FPGA resources, such as hardened DSP floating-point adder and multiplier primitives. For other AMD device families, the generated HDL code uses the full DSP mode to map the operators to the AMD floating-point IPs.
Data Types: char | string
Methods
Public Methods
createFloatingPointTargetConfig | Create floating-point target configuration for floating-point library that you specify |
Examples
Create Floating-Point Configuration with Native Floating Point and Generate Code
This example shows how to create a floating-point target configuration with the native floating-point support in HDL Coder, and then generate code.
Create a Floating-Point Target Configuration
To create a native floating-point configuration, use the hdlcoder.createFloatingPointTargetConfig function.
fpconfig = hdlcoder.createFloatingPointTargetConfig("NativeFloatingPoint")
fpconfig =
FloatingPointTargetConfig with properties:
Library: 'NATIVEFLOATINGPOINT'
LibrarySettings: [1x1 fpconfig.NFPLatencyDrivenMode]
IPConfig: [1x1 hdlcoder.FloatingPointTargetConfig.IPConfig]
VendorLibrary: []
VendorLibrarySettings: []
VendorIPConfig: []
Load the model, sfir_single.
load_system('sfir_single');
Specify Custom NFP Library Settings
To customize the native floating-point configuration, specify custom library settings.
fpconfig.LibrarySettings.HandleDenormals = 'off'; fpconfig.LibrarySettings.LatencyStrategy = 'MIN'; fpconfig.LibrarySettings.MantissaMultiplyStrategy = 'NoMultiplierFullAddShift'; fpconfig.LibrarySettings
ans =
NFPLatencyDrivenMode with properties:
LatencyStrategy: 'Min'
HandleDenormals: 'Off'
MantissaMultiplyStrategy: 'NoMultiplierFullAddShift'
PartAddShiftMultiplierSize: '18x24'
Version: '3.0.0'
View Latency of Native Floating-Point Operators
The IPConfig property stores an IPConfig object that displays the maximum and minimum latency values of the native floating-point operators.
fpconfig.IPConfig
ans =
Name DataType MaxLatency MinLatency CustomLatency
____________ _________________________ __________ __________ _____________
{'ABS' } {'DOUBLE' } 0 0 -1
{'ABS' } {'SINGLE' } 0 0 -1
{'ACOS' } {'SINGLE' } 23 17 -1
{'ACOSH' } {'SINGLE' } 93 93 -1
{'ADDSUB' } {'DOUBLE' } 11 6 -1
{'ADDSUB' } {'HALF' } 8 4 -1
{'ADDSUB' } {'SINGLE' } 11 6 -1
{'ASIN' } {'SINGLE' } 23 17 -1
{'ASINH' } {'SINGLE' } 94 94 -1
{'ATAN' } {'SINGLE' } 36 36 -1
{'ATAN2' } {'SINGLE' } 92 42 -1
{'ATANH' } {'SINGLE' } 67 67 -1
{'CONVERT' } {'DOUBLE_TO_NUMERICTYPE'} 6 3 -1
{'CONVERT' } {'DOUBLE_TO_SINGLE' } 6 3 -1
{'CONVERT' } {'HALF_TO_NUMERICTYPE' } 3 2 -1
{'CONVERT' } {'HALF_TO_SINGLE' } 2 1 -1
{'CONVERT' } {'NUMERICTYPE_TO_DOUBLE'} 6 3 -1
{'CONVERT' } {'NUMERICTYPE_TO_HALF' } 4 2 -1
{'CONVERT' } {'NUMERICTYPE_TO_SINGLE'} 6 6 -1
{'CONVERT' } {'SINGLE_TO_DOUBLE' } 5 3 -1
{'CONVERT' } {'SINGLE_TO_HALF' } 3 2 -1
{'CONVERT' } {'SINGLE_TO_NUMERICTYPE'} 6 6 -1
{'COS' } {'DOUBLE' } 48 48 -1
{'COS' } {'HALF' } 14 9 -1
{'COS' } {'SINGLE' } 27 27 -1
{'COSH' } {'SINGLE' } 27 17 -1
{'DIV' } {'DOUBLE' } 61 31 -1
{'DIV' } {'HALF' } 19 10 -1
{'DIV' } {'SINGLE' } 32 17 -1
{'EXP' } {'HALF' } 16 9 -1
{'EXP' } {'SINGLE' } 26 16 -1
{'FIX' } {'DOUBLE' } 5 3 -1
{'FIX' } {'SINGLE' } 5 3 -1
{'GAINPOW2'} {'DOUBLE' } 2 1 -1
{'GAINPOW2'} {'HALF' } 2 1 -1
{'GAINPOW2'} {'SINGLE' } 2 1 -1
{'HDLRECIP'} {'SINGLE' } 21 14 -1
{'HYPOT' } {'SINGLE' } 33 17 -1
{'LOG' } {'DOUBLE' } 44 34 -1
{'LOG' } {'HALF' } 17 9 -1
{'LOG' } {'SINGLE' } 27 20 -1
{'LOG10' } {'HALF' } 18 10 -1
{'LOG10' } {'SINGLE' } 27 17 -1
{'LOG2' } {'SINGLE' } 26 16 -1
{'MINMAX' } {'SINGLE' } 3 1 -1
{'MOD' } {'SINGLE' } 26 16 -1
{'MUL' } {'DOUBLE' } 9 6 -1
{'MUL' } {'HALF' } 6 4 -1
{'MUL' } {'SINGLE' } 8 6 -1
{'MULTADD' } {'SINGLE' } 14 8 -1
{'POW' } {'SINGLE' } 54 33 -1
{'POW10' } {'SINGLE' } 26 16 -1
{'POW2' } {'SINGLE' } 23 14 -1
{'RECIP' } {'DOUBLE' } 60 30 -1
{'RECIP' } {'HALF' } 19 10 -1
{'RECIP' } {'SINGLE' } 31 16 -1
{'RELOP' } {'DOUBLE' } 3 1 -1
{'RELOP' } {'HALF' } 2 1 -1
{'RELOP' } {'SINGLE' } 3 1 -1
{'REM' } {'SINGLE' } 24 15 -1
{'ROUNDING'} {'DOUBLE' } 5 3 -1
{'ROUNDING'} {'SINGLE' } 5 3 -1
{'RSQRT' } {'DOUBLE' } 59 33 -1
{'RSQRT' } {'SINGLE' } 30 16 -1
{'SIGNUM' } {'DOUBLE' } 0 0 -1
{'SIGNUM' } {'SINGLE' } 0 0 -1
{'SIN' } {'DOUBLE' } 34 34 -1
{'SIN' } {'HALF' } 14 8 -1
{'SIN' } {'SINGLE' } 27 27 -1
{'SINCOS' } {'SINGLE' } 27 27 -1
{'SINH' } {'SINGLE' } 30 18 -1
{'SQRT' } {'DOUBLE' } 58 36 -1
{'SQRT' } {'HALF' } 12 6 -1
{'SQRT' } {'SINGLE' } 28 16 -1
{'TAN' } {'SINGLE' } 33 33 -1
{'TANH' } {'SINGLE' } 43 25 -1
{'UMINUS' } {'DOUBLE' } 0 0 -1
{'UMINUS' } {'HALF' } 0 0 -1
{'UMINUS' } {'SINGLE' } 0 0 -1
Generate Code
For the sfir_single model, set the FloatingPointTargetConfiguration property to use the floating-point target configuration object, fpconfig.
hdlset_param('sfir_single',FloatingPointTargetConfiguration=fpconfig);
Generate HDL code by using the makehdl command. The generated code files are stored in the directory path specified by the TargetDirectory setting. In this example, the generated VHDL code is stored in the C:/NativeFloatingPoint/hdlsrc folder.
makehdl('sfir_single/symmetric_fir', ... TargetDirectory='C:/NativeFloatingPoint/hdlsrc')
### Working on the model <a href="matlab:open_system('sfir_single')">sfir_single</a>
### Generating HDL for <a href="matlab:open_system('sfir_single/symmetric_fir')">sfir_single/symmetric_fir</a>
### Using the config set for model <a href="matlab:configset.showParameterGroup('sfir_single', { 'HDL Code Generation' } )">sfir_single</a> for HDL code generation parameters.
### Running HDL checks on the model 'sfir_single'.
### Begin compilation of the model 'sfir_single'...
### Working on the model 'sfir_single'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 25 cycles.
### Output port 2: 25 cycles.
### Working on... <a href="matlab:configset.internal.open('sfir_single', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_sfir_single'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at <a href="matlab:open_system('C:/NativeFloatingPoint/hdlsrc/sfir_single/gm_sfir_single.slx')">C:/NativeFloatingPoint/hdlsrc/sfir_single/gm_sfir_single.slx</a>
### Begin VHDL Code Generation for 'sfir_single'.
### Working on sfir_single/symmetric_fir/nfp_add_single as C:/NativeFloatingPoint/hdlsrc/sfir_single/nfp_add_single.vhd.
### Working on sfir_single/symmetric_fir/nfp_mul_single as C:/NativeFloatingPoint/hdlsrc/sfir_single/nfp_mul_single.vhd.
### Working on sfir_single/symmetric_fir as C:/NativeFloatingPoint/hdlsrc/sfir_single/symmetric_fir.vhd.
### Generating package file C:/NativeFloatingPoint/hdlsrc/sfir_single/symmetric_fir_pkg.vhd.
### Code Generation for 'sfir_single' completed.
### Generating HTML files for code generation report at <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc24b_2725827_3881921/tp1ab0b3ec/hdlcoder-ex93289075/C:/NativeFloatingPoint/hdlsrc/sfir_single/html/sfir_single_codegen_rpt.html')">sfir_single_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc24b_2725827_3881921/tp1ab0b3ec/hdlcoder-ex93289075/C:/NativeFloatingPoint/hdlsrc/sfir_single/symmetric_fir_report.html
### HDL check for 'sfir_single' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
Create and Customize Mixed-Mode Floating-Point Configuration and Generate Code
This example shows how to create a mixed-mode floating-point target configuration with the native floating point (NFP) library and a vendor-specific floating point library in HDL Coder™ and generate code. The vendor library in this example is the Altera® Megafunctions (ALTERAFPFUNCTIONS) library.
Create a Floating-Point Target Configuration
To create a floating-point configuration, set up the path to your synthesis tool by using the hdlsetuptoolpathhdlsetuptoolpath command with the unique synthesis tool path on your computer. For example, the function quartuspath returns the Altera Quartus II synthesis tool path.
hdlsetuptoolpath('ToolName', 'Altera Quartus II','ToolPath', quartuspath);
Prepending following Altera Quartus II path(s) to the system path: B:\share\apps\HDLTools\Altera\21.1-mw-0\Windows\quartus\bin64
Load the model, sfir_single.
load_system('sfir_single')
Create a mixed-mode floating-point configuration, fpconfig, by using the function hdlcoder.createFloatingPointTargetConfig. The configuration fpconfig contains the NFP library and the Altera Megafunctions library configuration. Using NFP and vendor-specific IP together more efficiently uses resources on the FPGA, such as hardened DSP floating point adder or multiplier primitives, which allows you to fit a bigger design into the FPGA fabric.
fpconfig = hdlcoder.createFloatingPointTargetConfig("NativeFloatingPoint",VendorFloatingPointLibrary="ALTERAFPFUNCTIONS")
fpconfig =
FloatingPointTargetConfig with properties:
Library: 'NATIVEFLOATINGPOINT'
LibrarySettings: [1×1 fpconfig.NFPLatencyDrivenMode]
IPConfig: [1×1 hdlcoder.FloatingPointTargetConfig.IPConfig]
VendorLibrary: 'ALTERAFPFUNCTIONS'
VendorLibrarySettings: [1×1 fpconfig.FrequencyDrivenMode]
VendorIPConfig: [1×1 hdlcoder.FloatingPointTargetConfig.IPConfig]
Specify Custom NFP Library Settings
To customize the native floating-point configuration, specify custom library settings.
fpconfig.LibrarySettings.HandleDenormals = 'off'; fpconfig.LibrarySettings.LatencyStrategy = 'MIN'; fpconfig.LibrarySettings.MantissaMultiplyStrategy = 'NoMultiplierFullAddShift'; fpconfig.LibrarySettings
ans =
NFPLatencyDrivenMode with properties:
LatencyStrategy: 'Min'
HandleDenormals: 'Off'
MantissaMultiplyStrategy: 'NoMultiplierFullAddShift'
PartAddShiftMultiplierSize: '18x24'
Version: '3.0.0'
Specify Custom Vendor-Specific Library Settings
To customize the vendor-specific floating-point configuration, specify custom vendor library settings.
fpconfig.VendorLibrarySettings.InitializeIPPipelinesToZero = true; fpconfig.VendorLibrarySettings
ans =
FrequencyDrivenMode with properties:
InitializeIPPipelinesToZero: 1
View Latency of Floating-Point IPs
The IPConfig property stores an IPConfig object that displays the maximum and minimum latency values of the native floating-point operators.
fpconfig.IPConfig
ans =
Name DataType MaxLatency MinLatency CustomLatency
____________ _________________________ __________ __________ _____________
{'ABS' } {'DOUBLE' } 0 0 -1
{'ABS' } {'SINGLE' } 0 0 -1
{'ACOS' } {'SINGLE' } 23 17 -1
{'ACOSH' } {'SINGLE' } 93 93 -1
{'ADDSUB' } {'DOUBLE' } 11 6 -1
{'ADDSUB' } {'HALF' } 8 4 -1
{'ADDSUB' } {'SINGLE' } 11 6 -1
{'ASIN' } {'SINGLE' } 23 17 -1
{'ASINH' } {'SINGLE' } 94 94 -1
{'ATAN' } {'SINGLE' } 36 36 -1
{'ATAN2' } {'SINGLE' } 42 42 -1
{'ATANH' } {'SINGLE' } 67 67 -1
{'CONVERT' } {'DOUBLE_TO_NUMERICTYPE'} 6 3 -1
{'CONVERT' } {'DOUBLE_TO_SINGLE' } 6 3 -1
{'CONVERT' } {'HALF_TO_NUMERICTYPE' } 3 2 -1
{'CONVERT' } {'HALF_TO_SINGLE' } 2 1 -1
{'CONVERT' } {'NUMERICTYPE_TO_DOUBLE'} 6 3 -1
{'CONVERT' } {'NUMERICTYPE_TO_HALF' } 4 2 -1
{'CONVERT' } {'NUMERICTYPE_TO_SINGLE'} 6 6 -1
{'CONVERT' } {'SINGLE_TO_DOUBLE' } 5 3 -1
{'CONVERT' } {'SINGLE_TO_HALF' } 3 2 -1
{'CONVERT' } {'SINGLE_TO_NUMERICTYPE'} 6 6 -1
{'COS' } {'DOUBLE' } 48 48 -1
{'COS' } {'HALF' } 14 9 -1
{'COS' } {'SINGLE' } 27 27 -1
{'COSH' } {'SINGLE' } 27 17 -1
{'DIV' } {'DOUBLE' } 61 31 -1
{'DIV' } {'HALF' } 19 10 -1
{'DIV' } {'SINGLE' } 32 17 -1
{'EXP' } {'HALF' } 16 9 -1
{'EXP' } {'SINGLE' } 26 16 -1
{'FIX' } {'DOUBLE' } 5 3 -1
{'FIX' } {'SINGLE' } 5 3 -1
{'GAINPOW2'} {'DOUBLE' } 2 1 -1
{'GAINPOW2'} {'HALF' } 2 1 -1
{'GAINPOW2'} {'SINGLE' } 2 1 -1
{'HDLRECIP'} {'SINGLE' } 21 14 -1
{'HYPOT' } {'SINGLE' } 33 17 -1
{'LOG' } {'DOUBLE' } 44 34 -1
{'LOG' } {'HALF' } 17 9 -1
{'LOG' } {'SINGLE' } 27 20 -1
{'LOG10' } {'HALF' } 18 10 -1
{'LOG10' } {'SINGLE' } 27 17 -1
{'LOG2' } {'SINGLE' } 26 16 -1
{'MINMAX' } {'SINGLE' } 3 1 -1
{'MOD' } {'SINGLE' } 26 16 -1
{'MUL' } {'DOUBLE' } 9 6 -1
{'MUL' } {'HALF' } 6 4 -1
{'MUL' } {'SINGLE' } 8 6 -1
{'MULTADD' } {'SINGLE' } 14 8 -1
{'POW' } {'SINGLE' } 54 33 -1
{'POW10' } {'SINGLE' } 26 16 -1
{'POW2' } {'SINGLE' } 23 14 -1
{'RECIP' } {'DOUBLE' } 60 30 -1
{'RECIP' } {'HALF' } 19 10 -1
{'RECIP' } {'SINGLE' } 31 16 -1
{'RELOP' } {'DOUBLE' } 3 1 -1
{'RELOP' } {'HALF' } 2 1 -1
{'RELOP' } {'SINGLE' } 3 1 -1
{'REM' } {'SINGLE' } 24 15 -1
{'ROUNDING'} {'DOUBLE' } 5 3 -1
{'ROUNDING'} {'SINGLE' } 5 3 -1
{'RSQRT' } {'DOUBLE' } 59 33 -1
{'RSQRT' } {'SINGLE' } 30 16 -1
{'SIGNUM' } {'DOUBLE' } 0 0 -1
{'SIGNUM' } {'SINGLE' } 0 0 -1
{'SIN' } {'DOUBLE' } 34 34 -1
{'SIN' } {'HALF' } 14 8 -1
{'SIN' } {'SINGLE' } 27 27 -1
{'SINCOS' } {'SINGLE' } 27 27 -1
{'SINH' } {'SINGLE' } 30 18 -1
{'SQRT' } {'DOUBLE' } 58 36 -1
{'SQRT' } {'HALF' } 12 6 -1
{'SQRT' } {'SINGLE' } 28 16 -1
{'TAN' } {'SINGLE' } 33 33 -1
{'TANH' } {'SINGLE' } 43 25 -1
{'UMINUS' } {'DOUBLE' } 0 0 -1
{'UMINUS' } {'HALF' } 0 0 -1
{'UMINUS' } {'SINGLE' } 0 0 -1
The VendorIPConfig property stores an IPConfig object that displays the maximum and minimum latency values of the vendor-specific floating-point operators.
fpconfig.VendorIPConfig
ans =
Name DataType Latency ExtraArgs
___________ _________________________ _______ __________
{'ABS' } {'DOUBLE' } -1 {0×0 char}
{'ABS' } {'SINGLE' } -1 {0×0 char}
{'ADDSUB' } {'DOUBLE' } -1 {0×0 char}
{'ADDSUB' } {'SINGLE' } -1 {0×0 char}
{'CONVERT'} {'DOUBLE_TO_NUMERICTYPE'} -1 {0×0 char}
{'CONVERT'} {'NUMERICTYPE_TO_DOUBLE'} -1 {0×0 char}
{'CONVERT'} {'NUMERICTYPE_TO_SINGLE'} -1 {0×0 char}
{'CONVERT'} {'SINGLE_TO_NUMERICTYPE'} -1 {0×0 char}
{'COS' } {'DOUBLE' } -1 {0×0 char}
{'COS' } {'SINGLE' } -1 {0×0 char}
{'DIV' } {'DOUBLE' } -1 {0×0 char}
{'DIV' } {'SINGLE' } -1 {0×0 char}
{'EXP' } {'DOUBLE' } -1 {0×0 char}
{'EXP' } {'SINGLE' } -1 {0×0 char}
{'LOG' } {'DOUBLE' } -1 {0×0 char}
{'LOG' } {'SINGLE' } -1 {0×0 char}
{'MUL' } {'DOUBLE' } -1 {0×0 char}
{'MUL' } {'SINGLE' } -1 {0×0 char}
{'MULTADD'} {'SINGLE' } -1 {0×0 char}
{'RECIP' } {'DOUBLE' } -1 {0×0 char}
{'RECIP' } {'SINGLE' } -1 {0×0 char}
{'RELOP' } {'DOUBLE' } -1 {0×0 char}
{'RELOP' } {'SINGLE' } -1 {0×0 char}
{'RSQRT' } {'DOUBLE' } -1 {0×0 char}
{'RSQRT' } {'SINGLE' } -1 {0×0 char}
{'SIN' } {'DOUBLE' } -1 {0×0 char}
{'SIN' } {'SINGLE' } -1 {0×0 char}
{'SQRT' } {'DOUBLE' } -1 {0×0 char}
{'SQRT' } {'SINGLE' } -1 {0×0 char}
Customize Latency of ADDSUB Vendor IP
Using the customize method of either of the IPConfig objects, you can customize the latency of the floating-point IP and specify any additional arguments. In this example, customize the latency of the vendor IP by using the VendorIPConfig.customize method.
fpconfig.VendorIPConfig.customize('ADDSUB','Single','Latency',6); fpconfig.VendorIPConfig
ans =
Name DataType Latency ExtraArgs
___________ _________________________ _______ __________
{'ABS' } {'DOUBLE' } -1 {0×0 char}
{'ABS' } {'SINGLE' } -1 {0×0 char}
{'ADDSUB' } {'DOUBLE' } -1 {0×0 char}
{'ADDSUB' } {'SINGLE' } 6 {0×0 char}
{'CONVERT'} {'DOUBLE_TO_NUMERICTYPE'} -1 {0×0 char}
{'CONVERT'} {'NUMERICTYPE_TO_DOUBLE'} -1 {0×0 char}
{'CONVERT'} {'NUMERICTYPE_TO_SINGLE'} -1 {0×0 char}
{'CONVERT'} {'SINGLE_TO_NUMERICTYPE'} -1 {0×0 char}
{'COS' } {'DOUBLE' } -1 {0×0 char}
{'COS' } {'SINGLE' } -1 {0×0 char}
{'DIV' } {'DOUBLE' } -1 {0×0 char}
{'DIV' } {'SINGLE' } -1 {0×0 char}
{'EXP' } {'DOUBLE' } -1 {0×0 char}
{'EXP' } {'SINGLE' } -1 {0×0 char}
{'LOG' } {'DOUBLE' } -1 {0×0 char}
{'LOG' } {'SINGLE' } -1 {0×0 char}
{'MUL' } {'DOUBLE' } -1 {0×0 char}
{'MUL' } {'SINGLE' } -1 {0×0 char}
{'MULTADD'} {'SINGLE' } -1 {0×0 char}
{'RECIP' } {'DOUBLE' } -1 {0×0 char}
{'RECIP' } {'SINGLE' } -1 {0×0 char}
{'RELOP' } {'DOUBLE' } -1 {0×0 char}
{'RELOP' } {'SINGLE' } -1 {0×0 char}
{'RSQRT' } {'DOUBLE' } -1 {0×0 char}
{'RSQRT' } {'SINGLE' } -1 {0×0 char}
{'SIN' } {'DOUBLE' } -1 {0×0 char}
{'SIN' } {'SINGLE' } -1 {0×0 char}
{'SQRT' } {'DOUBLE' } -1 {0×0 char}
{'SQRT' } {'SINGLE' } -1 {0×0 char}
Generate Code
For the sfir_single model, set the FloatingPointTargetConfiguration property to use the floating-point target configuration object, fpconfig.
hdlset_param('sfir_single',FloatingPointTargetConfiguration=fpconfig);
Set the simulation library path in order to compile and simulate the generated code with your specified simulation tool.
hdlset_param('sfir_single','SimulationLibPath',alterasimulationlibpath);
Set the SynthesisToolChipFamily property to Arria10 and generate HDL code by using the makehdl command. The generated code files are stored in the directory path specified by TargetDirectory property. In this example, the generated VHDL code is stored in the C:/MixedModeFloatingPoint/hdlsrc folder.
makehdl('sfir_single/symmetric_fir',SynthesisToolChipFamily='Arria10',... TargetDirectory='C:/MixedModeFloatingPoint/hdlsrc')
### Generating HDL for 'sfir_single/symmetric_fir'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('sfir_single', { 'HDL Code Generation' } )">sfir_single</a> for HDL code generation parameters.
### Running HDL checks on the model 'sfir_single'.
### Begin compilation of the model 'sfir_single'...
### Working on the model 'sfir_single'...
### Using B:\share\apps\HDLTools\Altera\21.1-mw-0\Windows\quartus\bin64\..\sopc_builder\bin\ip-generate for the selected floating point IP library.
### Generating Altera(R) megafunction: alterafpf_mul_single for target frequency of 200 MHz.
### Found an existing generated file in a previous session: (C:\MixedModeFloatingPoint\hdlsrc\sfir_single\Altera\Arria10\unspecified\F200\synth\alterafpf_mul_single.vhd). Reusing the generated file.
### alterafpf_mul_single takes 3 cycles.
### Done.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 21 cycles.
### Output port 2: 21 cycles.
### Working on... <a href="matlab:configset.internal.open('sfir_single', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_sfir_single' ....
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generating Altera(R) megafunction: alterafpf_add_single for latency of 6.
### Found an existing generated file in a previous session: (C:\MixedModeFloatingPoint\hdlsrc\sfir_single\Altera\Arria10\unspecified\L6\synth\alterafpf_add_single.vhd). Reusing the generated file.
### Done.
### Begin VHDL Code Generation for 'sfir_single'.
### Working on sfir_single/symmetric_fir as C:\MixedModeFloatingPoint\hdlsrc\sfir_single\symmetric_fir.vhd.
### Generating package file C:\MixedModeFloatingPoint\hdlsrc\sfir_single\symmetric_fir_pkg.vhd.
### Code Generation for 'sfir_single' completed.
### Creating HDL Code Generation Check Report file:///C:/MixedModeFloatingPoint/hdlsrc/sfir_single/symmetric_fir_report.html
### HDL check for 'sfir_single' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
The latency of the ADDSUB IP is 6 and not the maximum latency value of 14.
Create a Floating-Point Target Configuration for AMD Floating-Point Library
This example shows how to create a floating-point target configuration with AMD floating-point operators.
To create a floating-point configuration, set the synthesis tool to Xilinx
Vivado and set the tool path for your synthesis tool using hdlsetuptoolpath function. For example,
hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath',... 'C:\Xilinx\Vivado\2023.1\bin\vivado.bat');
Create a floating-point target configuration object with
AMDFloatingPointOperators.
fpConfig = hdlcoder.createFloatingPointTargetConfig('AMDFloatingPointOperators')fpConfig =
FloatingPointTargetConfig with properties:
Library: 'NATIVEFLOATINGPOINT'
LibrarySettings: [1×1 fpconfig.NFPLatencyDrivenMode]
IPConfig: [1×1 hdlcoder.FloatingPointTargetConfig.IPConfig]
VendorLibrary: 'AMDFLOATINGPOINTOPERATORS'
VendorLibrarySettings: [1×1 fpconfig.AMDLatencyDrivenMode]
VendorIPConfig: [1×1 hdlcoder.FloatingPointTargetConfig.AMDIPConfig]In the vendor library setting of floating-point object, you can view the settings,
such as DSPSliceUsage, LatencyStrategy and
Objective, that are used to map your design to FPGA
resource.
fpConfig.VendorLibrarySettings
ans =
AMDLatencyDrivenMode with properties:
DSPSliceUsage: 'Primitive'
LatencyStrategy: 'Max'
Objective: 'Speed'DSPSliceUsage determines whether to map floating-point
operators in a primitive or full DSP mode, which depends on the FPGA device family. For
AMD Versal devices, floating-point operators can use
Primitive mode that map operators to the DSPFP32 or use
Full mode to map operators to DSP and logic fabrics. For
other AMD device families, floating-point operators are mapped to
Full mode.
fpConfig.VendorIPConfig
ans =
Name DataType MinLatency MaxLatency Latency ExtraArgs
____________________ __________ __________ __________ _______ __________
{'ADDSUB' } {'SINGLE'} 6 11 -1 {0×0 char}
{'ADDSUB_PRIMITIVE'} {'SINGLE'} 1 2 -1 {0×0 char}
{'MUL' } {'SINGLE'} 6 8 -1 {0×0 char}
{'MUL_PRIMITIVE' } {'SINGLE'} 1 3 -1 {0×0 char}Blocks other than these AMD floating-point operators are mapped to native floating-point operators.
Version History
Introduced in R2016bR2024b: Create vendor-specific AMD floating-point IP library
You can create designs and generate HDL code that utilizes the AMD floating-point library IPs. When you set the Synthesis Tool model configuration
parameter to Xilinx Vivado, you can create the floating-point
configuration for AMD floating-point library by setting
VendorFloatingPointLibrary to
AMDFloatingPointOperators, which enables the generation of code
that incorporates both AMD floating-point IP blocks and HDL Coder native floating-point IP blocks.
R2023a: createFloatingPointTargetConfig no longer supports creating objects with only vendor-specific floating-point libraries
You cannot create hdlcoder.FloatingPointTargetConfig objects that use
only vendor-specific floating-point libraries. You can create objects that use the native
floating-point library or that use both the native floating-point library and a
vendor-specific floating-point library.
If you load a model created before R2023a or a command-line script that creates an vendor-specific only floating-point IP configuration object, the object is converted to use both the vendor-specific library and the native floating-point library. The native floating-point settings are the default settings.
If you export an R2023a Simulink® model that uses both native floating-point and vendor-specific floating-point libraries to an earlier version of Simulink, the object uses only the native floating-point library and the vendor-specific settings are removed, such as the
VendorLibrary,VendorLibrarySettings, andVendorIPConfigsettings.
See Also
hdlcoder.FloatingPointTargetConfig.IPConfig | customize
Topics
- FPGA Floating-Point Library IP Mapping
- Floating Point Support: Field-Oriented Control Algorithm
- Generate HDL Code Using HDL Coder Native Floating Point and AMD Floating Point Library IP
- Floating-Point IPs
- Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries
- Customize Floating-Point IP Configuration
- Generate Target-Independent HDL Code with Native Floating-Point
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