Bits to Word

Convert vector of bits to integer

Since R2023a

• 

Libraries:
HDL Coder / Logic and Bit Operations

Description

The Bits to Word block converts a length-N input vector of bits to an N-bit integer. The output of the block is an unsigned integer that has word length N.

The block treats the first element of the input vector as the least significant bit (LSB) of the output and treats subsequent bits as the next significant bits in ascending order. This figure shows the conversion of the bit vector [1 0 1 1 0] to the integer value 13.

Examples

Convert Input Vector of Bits to Integer

Use the Bits to Word block in a Simulink® Model that converts vector of bits to an unsigned integer. You also generate HDL code for the model.

Open Script

Limitations

The block has these limitations:

• The input signal must have the ufix1 data type.

• Matrix input is not supported.

• Complex input is not supported.

• The input vector length cannot exceed 128.

Ports

Input

In — Input signal

binary-valued scalar | binary-valued vector

Input signal to the block, specified as binary-valued scalar or vector. You can specify an vector containing up to 128 elements.

Example: [0 1 1 0 0 1 1 1]

Data Types: fixdt(0,1,0)

Output

Out — Output signal

scalar

N-bit integer, where N is the size of the input vector, returned as a nonnegative scalar. For example, when you specify a 1-by-8 input signal, then the output signal is an unsigned integer with the ufix8 data type.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline.

Version History

Introduced in R2023a