Model Configuration Parameters: Optimization

The Optimization category enables you to specify various optimizations such as delay balancing, resource sharing and pipelining. To improve the area and timing of your design on the target hardware, specify these settings.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > General category.

Parameter	Description
Map pipeline delays to RAM	Map pipeline registers in the generated HDL code to RAM.
RAM mapping threshold	Specify the minimum RAM size for mapping to block RAMs.
Transform non zero initial value delay	Specify Transform Delay blocks to have zero initial value.
Remove Unused Ports	Remove unused ports from the design.
Enable-based constraints	Meet the timing requirement of the multicycle path in your model.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > Pipelining category.

Parameter	Description
Allow design delay distribution	Whether to allow distributed pipelining and delay absorption optimizations to move design delays.
Pipeline distribution priority	Priority for the distributed pipelining and delay absorption optimizations.
Clock-rate pipelining	Insert pipeline registers at a clock rate that is faster than the data rate.
Allow clock-rate pipelining of DUT output ports	Produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate.
Balance clock-rate pipelined DUT output ports	Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs.
Distributed pipelining	Enable pipeline register distribution.
Use synthesis estimates for distributed pipelining	Determine more accurate propagation delays for each component.
Adaptive pipelining	Insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.
Map lookup tables to RAM	Lookup tables in your design to block RAM and reduce area usage on the target FPGA device.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > Resource Sharing category.

Parameter	Description
Share Adders	Share adders with the resource sharing optimization.
Adder sharing minimum bitwidth	Specify the minimum bit width that is required to share adders with the resource sharing optimization.
Share Multipliers	Share multipliers with the resource sharing optimization.
Multiplier sharing minimum bitwidth	Specify the minimum bit width that is required to share multipliers with the resource sharing optimization.
Multiplier promotion threshold	Share smaller multipliers with other larger multipliers by using the resource sharing optimization.
Multiplier partitioning threshold	Partition multipliers based on a threshold.
Multiply-Add blocks	Share Multiply-Add blocks with the resource sharing optimization.
Multiply-Add block sharing minimum bitwidth	Specify the minimum bit width that is required to share Multiply-Add with the resource sharing optimization.
Atomic subsystems	Share Atomic Subsystem blocks with the resource sharing optimization.
MATLAB Function blocks	Share MATLAB Function blocks with the resource sharing optimization.
Floating-Point IPs	Share floating-point IPs in the design.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > Frame to Sample Conversion category.

Parameter	Description
Enable frame to sample conversion	Enable frame-to-sample conversion.
Samples per cycle	Specify the size of the signals after the frame-to-sample conversion streams them.
Input FIFO size	Specify the register size of the generated input FIFOs around the streaming matrix partitions.
Output FIFO size	Specify the register size of the generated output FIFOs around the streaming matrix partitions.
Input processing order	Choose between row-major and column-major ordering for the frame inputs.
Delay size threshold for external memory (bits)	Specify a threshold size in kilobytes to map large integer delays to input and output DUT ports and offload large delays to external memory outside of your FPGA.

The Configuration Parameters dialog box also includes other code generation parameters: