Workflow

Specify the target workflow

Model Configuration Pane: Target

Description

Specify your target workflow. The setting for this parameter determines the available parameters in the Target pane.

Settings

Generic ASIC/FPGA (Default) | IP Core Generation | FPGA-in-the-Loop | Simulink Real-Time FPGA I/O

The options are:

Generic ASIC/FPGA

Generate and verify HDL code from your Simulink^® model and synthesize the code for a specific ASIC or FPGA device.

IP Core Generation

Generate RTL code and a custom HDL IP core from your Simulink model. For more information, see Targeting FPGA & SoC Hardware Overview.

When you select IP Core Generation, the HDL Code tab in the Simulink Toolstrip updates to allow you to generate an IP core directly from the toolstrip. For more information, see Comparison of IP Core Generation Techniques.

The IP core is a shareable and modular HDL component that consists of IP core definition files, HDL code generated for your algorithm, a C header file with the register address map, and the IP core report. See:

You can select a hardware platform to generate IP core for from the platforms listed in HDL Language Support and Supported Third-Party Tools and Hardware.

FPGA-in-the-Loop

Test your Simulink model on a target FPGA. This setting requires HDL Verifier™ and the HDL Workflow Advisor.

Simulink Real-Time FPGA I/O

Generate HDL code from your Simulink model and deploy the code to Speedgoat^® FPGA I/O modules. This setting requires Xilinx^® Vivado^® and uses the same infrastructure as the IP Core Generation setting. For more information, see Simulink Real-Time FPGA I/O: Speedgoat Target Computer.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to store generated files and folders into a custom project folder for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods:

Pass the parameter as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','ProjectFolder','C:/Temp/hdlprj')

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ProjectFolder','C:/Temp/hdlprj')
makehdl('sfir_fixed/symmetric_fir')
```

Recommended Settings

No recommendations

Programmatic Use

Parameter: Workflow

Type: Character vector

Value: 'Generic ASIC/FPGA' | 'IP Core Generation' | 'FPGA-in-the-Loop' |

'Simulink Real-Time FPGA
                    I/O'

Default: 'Generic ASIC/FPGA'