Synthesis and Timing Analysis
|Set up system environment to access FPGA synthesis software|
- Structure of Generated Script Files
A generated EDA script consists of three sections, generated and executed in the following order:
- Properties for Controlling Script Generation
This section describes how to set properties in the
makehdltbfunctions to enable or disable script generation and customize the names and content of generated script files.
- Synthesis Objective to Tcl Command Mapping
Tool-specific Tcl commands that correspond to the HDL Workflow synthesis objectives.
- Generate Scripts for Compilation, Simulation, and Synthesis
Command line properties and GUI options for customizing script files
- Configure Compilation, Simulation, Synthesis, and Lint Scripts
You set options that configure script file generation on the EDA Tool Scripts pane.
- Add Synthesis Attributes
Synthesis attributes in generated code
- Configure Synthesis Project Using Tcl Script
Add Tcl script that configures your synthesis project