HDL Coder™ supports several optimizations, block implementations, and options that introduce discrete delays into your model, with the goal of more efficient hardware usage or achieving higher clock rates. Optimizations such as output pipelining, streaming, or resource sharing can introduce delays. Some block implementations, such as the Newton-Raphson and CORDIC architecture, inherently introduce delays in the generated code.
When optimizations or block implementation options introduce delays along the critical path in a model, the numerics of the original model and generated model or HDL code can differ because equivalent delays are not introduced on other, parallel signal paths. Manual insertion of compensating delays along other paths is possible, but is prone to error and does not scale well to large models that have many signal paths or multiple sample rates.
To avoid this issue, HDL Coder supports delay balancing. By default, delay balancing is enabled on the model. The code generator detects introduction of new delays along one path, and then inserts matching delays on the other paths. When you enable delay balancing, the generated model is functionally equivalent to the original model. It is not recommended that you disable delay balancing on the model. If you disable this setting, HDL Coder generates a warning that numeric differences can occur in the validation model. To fix this warning, enable Balance delays on the model or run the model check Check delay balancing setting.
You can set delay balancing for an entire model. For finer control, you can also set delay balancing for subsystems within the top-level DUT subsystem.
To set delay balancing for a model, use these
BalanceDelays: By default, model-level delay
balancing is enabled, and subsystems within the model inherit the
model-level setting. To learn how to set delay balancing for a model,
see Balance delays.
GenerateValidationModel: By default, validation
model generation is disabled. When you enable delay balancing, generate
a validation model to view delays and other differences between your
original model and the generated model. To learn how to enable
validation model generation, see the Generate
validation model section in Model Generation Parameters for HDL Code.
For example, these commands generate HDL code that has delay balancing and generate a validation model.
dut = 'ex_rsqrt_delaybalancing/Subsystem'; makehdl(dut,'BalanceDelays','on','GenerateValidationModel','on');
You can disable delay balancing for an entire model or disable it for a subsystem within the top-level DUT subsystem. For example, if you do not want to balance delays for a control path, you can put the control path in a subsystem, and then disable delay balancing for that subsystem.
To disable delay balancing for a subsystem within the top-level DUT subsystem, disable delay balancing at the model level. When you disable delay balancing for the model, the validation model does not compensate for latency inserted in the generated model due to optimizations or block implementations. The validation model can therefore show mismatches between the original model and generated model.
To disable delay balancing for a subsystem within the top-level DUT subsystem:
Disable delay balancing for the model.
Enable delay balancing for the top-level DUT subsystem.
Disable delay balancing for a subsystem within the DUT subsystem.
When delay balancing is enabled on the model, the delay balancing setting on individual subsystems is ignored. To learn how to set delay balancing for a subsystem, see Set Delay Balancing For a Subsystem.
When you generate HDL code, delay balancing is an essential part of code
optimizations. If any optimizations are enabled, you must balance pipelines
introduced as a part of those optimizations. Failure to balance automatically
inserted pipeline delays causes issues in generated code deployed in hardware. The
recommended way to balance these delays is to keep
on for the model (its default).
When you disable delay balancing for the model, or at some specific subsystems, HDL Coder does not compensate for latency inserted due to optimizations or block implementations. Unbalanced delays can lead to a mismatch in simulation results between HDL code and your Simulink model and unexpected and untested behavior of hardware implementation. It is recommended that you generate the validation model and observe effects of such unbalanced delays. For examples of delay balancing and the validation model, see Delay Balancing and Validation Model Workflow In HDL Coder™ and Resolve Numeric Mismatch with Delay Balancing.
For some multirate models, HDL Coder might generate a large number of pipeline registers that can prevent the HDL design from fitting into an FPGA. Before you disable delay balancing for the model to try to solve this issue, see Delay Balancing on Multi-Rate designs and Optimize Generated HDL Code for Multirate Designs with Large Rate Differentials.
If delay balancing is disabled for your model:
When turning off
BalanceDelays, also turn off any
features that generate pipelines or add latency, such as optimizations
like resource sharing, streaming, pipelining, or enabling the
MapToRAM HDL block property of a lookup table
(LUT) block. Manually balance the delays instead. For more information,
see Resource Sharing For Area Optimization,
Streaming: Area Optimization,
Distributed Pipelining: Speed Optimization,
Use local delay balancing where possible in your model to save time on manually balancing delays for your entire DUT. For more information on how to apply local delay balancing to specific parts of your model, see Control the Scope of Delay Balancing and Set Delay Balancing For a Subsystem.
Check for the command-line messages about additional latency, such as
The code generation and optimization options you have
chosen have introduced additional pipeline delays, and
remove optimization settings that insert latency. For an example, see
Delay Balancing and Validation Model Workflow In HDL Coder™.
Check for blocks that have nonzero output
latency Model Advisor check. For more information, see
Check for blocks that have nonzero output latency.
There might be some use cases where you must turn off global delay balancing. To disable delay balancing for the model:
BalanceDelays option for your model at
the command line. See Command-Line Information.
Starting in R2021b, the
BalanceDelays option is no
longer a global option in the model configuration parameters.
Change the diagnostic option
None. This option
BalanceDelays is set to off and there
are unbalanced delays in the model as a result. For more information,
see Check for presence of unbalanced delays in generated HDL code.
If delay balancing is unsuccessful,
cannot optimize the generated HDL code.
The following blocks and subsystems do not support delay balancing:
Data Type Duplicate
Decrement To Zero
FFT HDL Optimized
To VCD File
Magnitude-Angle to Complex
Blocks that have
NoHDL architecture do not support
HDL Coder does not support delay balancing, if:
The BalanceDelays block property for all instances of an Atomic Subsystem or Model Reference resolves to a different value.
To fix this error, disable
all instances of the Atomic
Subsystem or Model Reference.
The block is inside a conditional subsystem and has pipeline delays.
A subsystem with
Architecture has the
ImplementationLatency block property set to a
To fix this error, for ImplementationLatency, enter a nonnegative integer.
HDL Coder does not support delay balancing, if:
Delays are introduced in a feedback loop and HDL Coder cannot balance the path delays. For example, if you apply clock-rate pipelining inside a feedback loop, HDL Coder introduces a delay at the clock-rate, and can cause delay balancing to fail.
To reduce the number of clock-rate delays, increase the Oversampling factor.
The sample time is not discrete or the ratio of sample times of the fastest to the slowest rate is too large.
When you have Constant blocks as inputs inside the DUT
Subsystem for which delay balancing is enabled, you see an initial simulation
mismatch in the validation model. Consider this model inside a DUT Subsystem.
The Constant block that outputs a value of
has the HDL block property OutputPipeline set to
This figure displays the generated validation model. You see that delay
balancing added a matching delay to the input port to balance the pipeline
register inserted for the Delay block. The code generator does
not insert a matching delay on the parallel path containing the
Constant block with the value
the output value of the block is a constant. This delay not inserted results in
an initial simulation mismatch.
To resolve the simulation mismatch, in the validation model, manually add a
matching delay at the output of the Constant block with the value
To see the delay balancing information in the report, before you generate code for each subsystem or model reference, enable the optimization report. In the HDL Code Generation tab, select Report, and then select Generate optimization report.
When you generate code for each subsystem, model reference, or MATLAB Function block, HDL Coder produces the optimization report. Select the Delay Balancing section of the report.
The Delay Balancing Report shows latency changes, pipeline and phase delay at the output ports, and the number of pipelines added at the output ports to match the delays. If delay balancing fails, the report displays the criteria that was violated and the link to any block or subsystem that caused delay balancing to fail.