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Generate HDL Code for Simscape Models

This example shows how to generate HDL code for a half-wave rectifier model that uses Simscape™ blocks. Use the Simscape HDL Workflow Advisor to generate an HDL implementation model. You can then generate HDL code for the implementation model. See Get Started with Simscape Hardware-in-the-Loop Workflow.

The Halfwave Rectifier Model

To open the half-wave rectifier model, at the MATLAB® command prompt, enter:


Save this model locally as HalfWaveRectifier_HDL to run the workflow.

set_param('HalfWaveRectifier_HDL', 'SimulationCommand', 'Update')

At the top level of the model, a Simscape_system block models the half-wave rectifier algorithm. The model accepts a Sine Wave input, uses a Rate Transition block to discretize the continuous time input, and has a Scope block that calculates the output. To see the half-wave rectifier algorithm, double-click the Simscape_system subsystem.


The half-wave rectifier consists of a resistor, which is a linear block, and a diode, which is a switched linear block. The Simscape model is preconfigured for HDL compatibility. At the input and output port interfaces, the model has Simulink-PS Converter and PS-Simulink Converter blocks. The solver settings are configured for compatibility with Simscape HDL Workflow Advisor. If you open the Block Parameters dialog box for the Solver Configuration block, Use local solver is selected and Backward Euler is specified as the Solver type. See Get Started with Simscape Hardware-in-the-Loop Workflow.

To see the functionality, simulate the model and then open the Scope block.


Run Simscape HDL Workflow Advisor

To generate an HDL implementation model from which you generate code, use the Simscape HDL Workflow Advisor. To open the Advisor, run this command:


This command updates the model advisor cache and opens the Simscape HDL Workflow Advisor. To learn more about the Simscape HDL Workflow Advisor and the various tasks, right-click that folder or task, and select What's This?. See also Simscape HDL Workflow Advisor Tasks.

To run the workflow and compare functionality of the HDL implementation model with the original Simscape algorithm, select the Generate implementation model step, and then select the Generate validation logic for the implementation model check box. Use a Validation logic tolerance of 0.001. Right-click the Generate implementation model step and select Run to Selected Task.

The Advisor generates an HDL implementation model and a state-space validation model. The implementation model has the same name as the original Simscape model and uses the prefix gmStateSpaceHDL_. The state-space validation model has the same name as the implementation model and uses the postfix _vnl.

Open and Examine HDL Implementation Model

In the Generate implementation model task, click the link to open the implementation model. The model contains a Simscape_system subsystem that contains a HDL Subsystem block. The HDL Subsystem models the state-space representation that you generated from the Simscape model.


The ports of this subsystem use the same name as the Simulink-PS Converter and PS-Simulink Converter blocks in your original Simscape model. If you navigate inside this subsystem, you see several delays, adders, and Matrix Multiply blocks that model the state-space equations.

open_system('gmStateSpaceHDL_HalfWaveRectifier_HDL/Simscape_system/HDL Subsystem/HDL Algorithm')

To simulate the HDL Implementation model, enter these commands. Open the Scope block to view results.


HDL code is generated for the HDL Subsystem block inside this model.

Validate HDL Algorithm

To compare functionality of the HDL implementation model with the original Simscape algorithm, open and simulate the state-space validation model.


The output of this model matches the original Simscape model. The simulation does not generate assertions, which indicates that the outputs match. For a more systemic verification, see Validate HDL Implementation Model to Simscape Algorithm.

Generate HDL Code and Validation Model

The HDL model and subsystem parameter settings are saved using this command:

%% Set Model 'gmStateSpaceHDL_HalfWaveRectifier_HDL' HDL parameters
hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL', 'FPToleranceValue', 1.000000e-03);
fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT' ...
, 'LatencyStrategy', 'Min' ...
hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL', 'FloatingPointTargetConfiguration', fpconfig);
hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL', 'HDLSubsystem', 'gmStateSpaceHDL_HalfWaveRectifier_HDL/Simscape_system/HDL Subsystem');
hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL', 'MaskParameterAsGeneric', 'on');
hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL', 'Oversampling', 13);
hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL', 'UseFloatingPoint', 'on');

hdlset_param('gmStateSpaceHDL_HalfWaveRectifier_HDL/Simscape_system/HDL Subsystem/HDL Algorithm/Mode Selection/Generate Mode Vector', 'Architecture', 'MATLAB Datapath');

The model uses single data types and generates HDL code in Native Floating Point mode. Floating-point operators can introduce delays. Because the design contains feedback loops, to allocate sufficient delays for the operators inside the feedback loops, the model uses clock-rate pipelining.

For more information, see:

Before you generate HDL code, enable generation of the validation model. The validation model compares the output of the generated model after code generation and the original model. To learn more, see Generated Model and Validation Model.

Run these commands to save validation model generation settings on your Simulink model:

HDLmodelname = 'gmStateSpaceHDL_HalfWaveRectifier_HDL';
hdlset_param(HDLmodelname, 'TargetDirectory', 'C:/Temp/hdlsrc');
hdlset_param(HDLmodelname, 'GenerateValidationModel', 'on');

To generate HDL code, run this command:

makehdl('gmStateSpaceHDL_HalfWaveRectifier_HDL/Simscape_system/HDL Subsystem');

The generated HDL code and validation model are saved in C:/Temp/hdlsrc directory. The generated code is saved as HDL_Subsystem.vhd. To open the validation model, click the link to gm_gmStateSpaceHDL_HalfWaveRectifier_HDL_vnl.slx in the code generation logs in the Command Window.

Open the Compare block at the output of HDL Subsystem_vnl subsystem of the validation model. To see the simulation results after HDL code generation, double-click the Double click to turn 'on/off' all scopes block. For each of the scopes (IR, Iout, and Vdiode), the first graph represents the output of the generated model, and the middle graph represents the output of the implementation model. The bottom graph calculates the difference between outputs of both models. As the outputs match, the error is zero.

See Also


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