DPI Generation for Simulink Subsystem

Generate SystemVerilog DPI component from Simulink® subsystem

You can use a DPI component generated from a Simulink subsystem in two ways :

  • Export SystemVerilog DPI Component — You can integrate this component into your HDL simulation as a behavioral model. The component generator supports test points and tunable parameters. You can also generate a SystemVerilog testbench that verifies the generated DPI component against data vectors from your subsystem. See Generate SystemVerilog DPI Component.

  • Generate SystemVerilog DPI Testbench (with HDL Coder™) — Use this testbench to verify your generated HDL code using C code generated from your entire Simulink model, including the DUT and data sources. See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).

See DPI Component Generation with Simulink.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.

Not all DPI generation functionalities are available in MATLAB® Online™.

Apps

HDL VerifierGenerate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)

Blocks

AssertionGenerate SystemVerilog assertions from Simulink assertion

Model Settings

Customize generated SystemVerilog codeChoice to customize the generated SystemVerilog code
Source file template:File name and location of the template you want to use for customizing the generated SystemVerilog code
Report run-time errorExports run-time errors
SeveritySeverity for run-time errors
Generate test benchGenerates a testbench for the DPI component
Floating point toleranceNumeric tolerance when comparing floating point values from Simulink output with the DPI component outputs running in the HDL simulator (Since R2025a)
HDL simulatorHDL simulator to use when simulating the testbench in MATLAB
Generate access function to test pointType of test point access functions to generate in the SystemVerilog DPI component
Ports data typeSystemVerilog data type that will be used for ports that have fixed-point data
ConnectionHow signals are connected when the module is instantiated
Composite data typeHow the SystemVerilog ports are generated when your Simulink model includes a port which is a Nonvirtual bus or a complex data type
Scalarize matrix and vector portsChoice for how ports are generated when your Simulink model includes a port which is an array or matrix data type
Component template typeTemplate for SystemVerilog DPI generation

Topics

Generate and Verify a DPI Component

Advanced DPI Options

Verify Generated HDL Code with SystemVerilog DPI Testbench (requires HDL Coder license)

Featured Examples

Build HDL Testbench for QAM Transceiver Model

Build HDL Testbench for QAM Transceiver Model

Build a behavioral testbench using SystemVerilog DPI-C component generation. This testbench is used for the verification of synthesizable HDL code of a 64-QAM transmitter and receiver.

Verify Standalone CTLE in Architectural, Behavioral, and Circuit Domains

Verify Standalone CTLE in Architectural, Behavioral, and Circuit Domains

Simulates a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation. The Simulink® architectural model acts as a high-level specification of the desired analog circuit behavior. Using HDL Verifier™, export the standalone CTLE model into a SystemVerilog behavioral model. The exported model enables early digital control development for analog calibration before you design the analog circuit. A circuit implementation of the CTLE is characterized (offline) using analog simulations. The characterization results are then fed back into the architectural model. This converts the specification-based Simulink model into a circuit-representative model. Both specification and circuit-representative models of the CTLE are provided as part of this example. Use HDL Verifier to regenerate the SystemVerilog behavioral model. This model can be used for mixed-signal validation; turning the specification-based SystemVerilog model into a circuit-representative SystemVerilog model. This automation keeps the architectural, behavioral, and circuit models in synchronicity.

Verify SerDes Toolbox CTLE in Architectural, Behavioral, and Circuit Domains

Verify SerDes Toolbox CTLE in Architectural, Behavioral, and Circuit Domains

Demonstrates a workflow to simulate a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation.

Verify Multi-Path ADC in Architectural, Behavioral, and Circuit Domains

Verify Multi-Path ADC in Architectural, Behavioral, and Circuit Domains

Use a time-interleaved analog to digital converter (ADC) from Mixed-Signal Blockset™ to develop an offset and gain calibration engine for mismatched interleaved ADC paths. For an architectural representation of time-interleaved ADC for IBIS-AMI export, see the ADC IBIS-AMI Model based on COM and Architectural 112G PAM4 ADC-Based SerDes Model examples.

Generate HDL for Dual-Summing-Node DFE

Generate HDL for Dual-Summing-Node DFE

Design a bit-accurate decision feedback equalizer (DFE) adaptation engine for an architecturally representative 100-Gb/s dual-summing-node-DFE PAM4 SerDes receiver model using blocks from the SerDes Toolbox™. This bit-accurate DFE adaptation engine generates synthesizable RTL code that is suitable for implementation in an ASIC or an FPGA. The implementation-representative datapath in the DFE model enables the adaptation engine to reflect key design aspects: PAM4 threshold recovery, DFE tap weight adjustment, and clock phase sensitivity.

Generate Bit Vector and Logic Vector Data Types

Generate Bit Vector and Logic Vector Data Types

Generate bit or logic vector data types in the SystemVerilog interface of the DPI component. This capability is useful whenever having an exact width of the port is important to integrate the DPI component in your testbench.

Getting Started with Customizing Generated SystemVerilog Code

Getting Started with Customizing Generated SystemVerilog Code

Customize the generated SystemVerilog code in the SystemVerilog DPI Component Generation process.

Generate Native SystemVerilog Assertions from Simulink

Generate Native SystemVerilog Assertions from Simulink

Generate native SystemVerilog assertions from assertions in a Simulink® model. This capability is useful whenever you need the same assertion behavior in Simulink and in your HDL testing environment.

Generating Functional Coverage in SystemVerilog from Simulink Test verify Calls

Generating Functional Coverage in SystemVerilog from Simulink Test verify Calls

Demonstrates how to test a projector control system using model simulation, and how to generate a SystemVerilog DPI component for some of the controller's high level requirements that are specified in a Test Sequence block. This will allow the requirement verification used for model simulation to be reused in the HDL simulator with minimal effort.

Verify 5G Wireless Applications Using SystemVerilog DPI

Verify 5G Wireless Applications Using SystemVerilog DPI

Use SystemVerilog DPI components to verify 5G wireless applications in an HDL environment.

Integrate SystemVerilog DPI into UVM Framework Workflow

Integrate SystemVerilog DPI into UVM Framework Workflow

Generate reusable verification components from a Simulink® model as SystemVerilog DPI components using HDL Verifier™ software. You use the MATLAB-to-UVMF (mtlb2uvmf) workflow to create Universal Verification Methodology (UVM) testbenches quickly. For more information on mtlb2uvmf workflow, see MathWorks Integration from Siemens Verification Academy.