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DPI Generation for Simulink Subsystem

Generate SystemVerilog DPI component from Simulink® subsystem

You can use a DPI component generated from a Simulink subsystem in two ways :

  • Export SystemVerilog DPI Component — You can integrate this component into your HDL simulation as a behavioral model. The component generator supports test points and tunable parameters. You can also generate a SystemVerilog testbench that verifies the generated DPI component against data vectors from your subsystem. See Generate SystemVerilog DPI Component.

  • Generate SystemVerilog DPI Testbench (with HDL Coder™) — Use this testbench to verify your generated HDL code using C code generated from your entire Simulink model, including the DUT and data sources. See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).

See DPI Component Generation with Simulink.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.

Not all DPI generation functionalities are available in MATLAB® Online™.

Apps

HDL VerifierGenerate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)

Blocks

AssertionGenerate SystemVerilog assertions from Simulink assertion

Model Settings

Customize generated SystemVerilog codeChoice to customize the generated SystemVerilog code
Source file template:File name and location of the template you want to use for customizing the generated SystemVerilog code
Report run-time errorExports run-time errors
SeveritySeverity for run-time errors
Generate test benchGenerates a testbench for the DPI component
Floating point toleranceNumeric tolerance when comparing floating point values from Simulink output with the DPI component outputs running in the HDL simulator (Since R2025a)
HDL simulatorHDL simulator to use when simulating the testbench in MATLAB
Generate access function to test pointType of test point access functions to generate in the SystemVerilog DPI component
Ports data typeSystemVerilog data type that will be used for ports that have fixed-point data
ConnectionHow signals are connected when the module is instantiated
Composite data typeHow the SystemVerilog ports are generated when your Simulink model includes a port which is a Nonvirtual bus or a complex data type
Scalarize matrix and vector portsChoice for how ports are generated when your Simulink model includes a port which is an array or matrix data type
Component template typeTemplate for SystemVerilog DPI generation

Topics

Generate and Verify a DPI Component

Advanced DPI Options

Verify Generated HDL Code with SystemVerilog DPI Testbench (requires HDL Coder license)

Featured Examples