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Configure operator that combines individual signal value comparisons into overall capture condition

Since R2022a



setCaptureConditionCombinationOperator(DC,operator) configures the logical operator operator that combines comparisons of individual signals into an overall capture condition. DC is a customized data capture object.


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This example uses a customized data capture object, DC, that defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic.

DC.EnableCaptureCtrl = true;

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IP core using the FPGA Data Capture Component Generator tool.

Set up a capture condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is equal to 17.


Combine comparisons of signals A and B into an overall capture condition using an AND operator.


Input Arguments

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Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Logical operator to combine comparisons of individual signals into a capture condition, specified as 'AND' or 'OR'. The capture condition comprises value comparisons of one or more signals. To combine value comparisons, you can use only one type of logical operator. For example, suppose three signals, A, B, and C, make up the capture condition. The options are:

  • A == 10 AND B == 'Falling edge' AND C == 0
  • A == 10 OR B == 'Falling edge' OR C == 0

You cannot mix and match the combination operators. For details on capture conditions, see Capture Conditions.

Version History

Introduced in R2022a