uvmbuild

Generate UVM testbench from Simulink model

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Add-On Required: This feature requires the ASIC Testbench for HDL Verifier add-on.

Syntax

uvmbuild(dut,sequence,scoreboard)
uvmbuild(___,Name,Value)

Description

uvmbuild(dut,sequence,scoreboard) generates a SystemVerilog top module, which includes a universal verification methodology (UVM) testbench and a behavioral design under test (DUT). The UVM testbench includes a sequence, a scoreboard, monitors, and drivers. The uvmbuild function maps:

  • The Simulink® DUT subsystem to a generated SystemVerilog DPI behavioral DUT

  • The Simulink sequence subsystem to a UVM sequence block

  • The Simulink scoreboard subsystem to a UVM scoreboard

The uvmbuild function supports these HDL simulators:

  • Siemens® Questa™

  • Siemens ModelSim™

  • Synopsys® VCS® (Supported on Linux® or cross-platform workflows)

  • Cadence® Xcelium™ (Supported on Linux or cross-platform workflows)

For cross platform support, see Generate Cross-Platform UVM Components.

example

uvmbuild(___,Name,Value) specifies options using one or more name-value pair arguments in addition to the input arguments in the previous syntax. For example, 'Driver','mySLTopModule/myDriver' generates a UVM driver from the Simulink subsystem specified as 'mySLTopModule/myDriver'.

Examples

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This example uses:

Open Model

Simulink Model Structure

This example uses a Simulink® model, that includes these three subsystems.

  • A sequence subsystem, which generates stimulus for the DUT.

  • A DUT subsystem, which represents your HDL design.

  • A scoreboard subsystem, which collects the outputs and checks them. In this example the DUT is a simple delay block.

open_system('hdlv_uvmbuild');

Generate UVM Testbench

Generate a UVM testbench from this Simulink model, specifying the paths to the DUT, sequence, and scoreboard subsystems.

uvmbuild('hdlv_uvmbuild/DUT','hdlv_uvmbuild/Sequence','hdlv_uvmbuild/Scoreboard');

Observe Generated Output

The uvmbuild function creates a directory named hdlv_uvmbuild_uvmbuild containing the uvm_testbench directory. The uvm_testbench directory includes these subdirectories.

  • The top directory includes a SystemVerilog top module and generated scripts to execute in your HDL simulation environment.

  • The DPI_dut directory contains the SystemVerilog-DPI behavioral DUT.

  • The sequence directory contains the generated sequence transaction type and a UVM sequencer, which drives the transaction to the DUT.

  • The scoreboard directory contains the generated UVM scoreboard.

  • The uvm_artifacts directory contains UVM components, such as monitors, drivers, and agents, required for the UVM environment.

Run Generated UVM Testbench

  1. Start Modelsim® or Questasim in GUI mode.

  2. In the HDL simulator, navigate to the top directory: cd hdlv_uvmbuild_uvmbuild\uvm_testbench\top\

  3. In the HDL simulator, enter this command to run your simulation: do run_tb_mq.do

Input Arguments

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Design under test subsystem, specified as a character vector or string scalar representing a DUT-subsystem name or full block path.

Example: 'hdlv_uvmbuild/DUT'

Data Types: char | string

Sequence subsystem, specified as a character vector or string scalar representing a sequence-subsystem name or full block path.

Example: 'hdlv_uvmbuild/sequence'

Data Types: char | string

Scoreboard subsystem, specified as a character vector or string scalar representing a scoreboard-subsystem name or full block path.

Example: 'hdlv_uvmbuild/scoreboard'

Data Types: char | string

Name-Value Arguments

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Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: uvmbuild('top/dut','top/seq','top/scr','Driver','top/drv','Monitor','top/mon')

Driver subsystem, specified as a character vector or string scalar representing a driver-subsystem name or full block path. By default, the uvmbuild function generates a passthrough UVM driver.

Example: 'hdlv_uvmbuild/driver'

Data Types: char | string

Monitor subsystem, specified as a character vector or string scalar representing a monitor-subsystem name or full block path. By default, the uvmbuild function generates a passthrough UVM monitor.

Example: 'hdlv_uvmbuild/monitor'

Data Types: char | string

Predictor subsystem, specified as a character vector or string scalar representing a predictor subsystem name or full block path.

Example: 'hdlv_uvmbuild/predictor'

Data Types: char | string

UVM configuration parameters, specified as the comma-separated pair consisting of 'Config' and a uvmcodegen.uvmconfig configuration object. Use this value to configure the generated UVM testbench.

Data Types: char | string

Sequence Feedback block, specified as a character vector or string scalar representing a Sequence Feedback block name or full block path. For multiple Sequence Feedback blocks, use a cell array.

Example: 'hdlv_uvmbuild/feedback'

Example: {'hdlv_uvmbuild/feedback1','hdlv_uvmbuild/feedback2','hdlv_uvmbuild/feedback3'}

Data Types: char | string

Version History

Introduced in R2019b

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See Also

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