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Implement Memory Map with SCML

What Is SCML?

The SystemC™ Modeling Library (SCML) is a TLM 2.0 compatible API library for creating TLM model interfaces for use with Synopsys® prototyping tools. These tools enable early software integration and testing. The SCML interface provides backdoor register access for the Synopsys tools during simulation. Use HDL Verifier™ software to export a TLM component with an SCML interface for seamless use with the Synopsys prototyping tools.



This feature requires the ASIC Testbench for HDL Verifier add-on.

To generate a TLM component with SCML memory map:

  1. Install SCML. You can download SCML from Synopsys, see

  2. Open Configuration Parameters>Code Generation>TLM Generator. See Select TLM Generator System Target.

  3. On the TLM Mapping tab, provide an IP-XACT file describing the memory map of your component. Then select the SCML option. See Select TLM Mapping Options.

  4. Specify the location of your SCML installation on the TLM Compilation tab. See Select TLM Compilation Options.

  5. Generate code for your model as you would for any other model. See Generate Component and Test Bench.

Generated Code

When you generate code for your model, the TLM generator creates the same set of files to implement the TLM component as it would without SCML. The files are named SystemName_scml rather than SystemName_tlm.

SCML supports bit widths of 8, 16, 32, 64, 128, and 256. When generating the SCML interface for Simulink® signals, the generator rounds up to the next supported size.

IP-XACT classes are translated to SCML classes according to this mapping.


The SCML interface has no effect on test bench generation for the TLM component. The test bench does not use the SCML access functions.

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