Design and Evaluate Simple PLL Model
This example shows how to design a simple phase-locked loop (PLL) using a reference architecture and validate it using PLL Testbench.
A PLL is a frequency synthesizer system that produces an output signal whose phase depends on the phase of its input signal. In the simplest form, a PLL consists of a phase/frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and a clock divider in a feedback loop. The PFD and charge pump together produce an error signal proportional to the phase difference of its two input signals. The loop filter removes the higher-frequency components of the error signal, which drives the VCO. The output of the VCO is fed through a clock divider to the input of the PFD, producing a negative feedback loop.
Mixed-Signal Blockset™ provides reference architectures to design a simple PLL model and testbenches to verify that the designed model meets the design specifications.
Set Up PLL Testbench Model
Open the model
simplePLL attached to this example as a supporting file. The model consists of an Integer N PLL with Single Modulus Prescaler block and a PLL Testbench block.
PLL Specifications and Impairment
Use the data sheet of Skyworks SKY73134-11 to design the PLL system to lock at 2.8 GHz.
Double-click the Integer N PLL with Single Modulus Prescaler block to open the Block Parameters dialog box and verify these settings: * Check that the impairments are disabled in the PFD and Charge pump tabs. * In the Charge pump tab, the Output current is set to
2.7 mA. The Deadband compensation and Input threshold parameters are kept at default values.
In the VCO tab, the VCO Sensitivity is set to
20MHz/V. The Free running frequency is slightly lower than the target lock frequency and is set to
2.78GHz. The Phase noise frequency offset is set to
[100e3 1e6 3e6 10e6]Hz and the Phase noise level (dBc/Hz) is set to
[−108 −134 −145 −154]dBc/Hz.
Considering the reference input frequency to the PLL is
1.6MHz, the Clock divider value and the Min clock divider value in the Prescaler tab is set to .
In the Loop Filter tab, the Loop bandwidth is set to
160kHz, 1/10th of the reference input frequency. The phase margin is kept at default 45 degrees. Filter component values are calculated automatically.
In the Analysis tab, both Open Loop Analysis and Closed Loop Analysis plots are selected.
Plot Presimulation PLL Loop Dynamics
Click the Plot Loop Dynamics button to view the presimulation results and aseess the stability of the system.
The closed loop analysis consists of the Pole-Zero Map, Magnitude Response, Step Response, and Impulse Response. The 3-dB bandwidth of the system is
288.51 kHz. The system is stable.
The open loop analysis consists of Bode plots of the PLL system. The phase margin is
44.1 degrees and the unity gain frequency is
Modify PLL Testbench for Phase Noise Measurement
Double-click the PLL Testbench to open the Block Parameters dialog box and verify these settings: * In the Stimulus tab, the input signal to the PLL is defined as a square wave of
In the Setup tab, check that the Phase noise measurement option is selected. Frequency of operation and Lock time measurement options are deselected. Set the Resolution bandwidth to
50kHz, No. of spectral averages to
4and Hold off time to
In the Target Metrics tab, set the Phase noise (dBc/Hz) to
[−108 −134 −145 −154], the same as the PLL phase noise profile.
Plot PLL Phase Noise Profile
Run the simulation for
1.35e-4 s. The simulation results are displayed on the icon of the PLL Testbench. The measured phase noise levels at specific frequency offsets are consistent with their target values.
Double-click the PLL Testbench block to open the Block Parameters dialog box. Click the Plot phase noise profile button. The PLL operating frequency is
2.8 GHz, and the measured phase noise profile matches the target profile.