Design and Evaluate Simple PLL Model

This example shows how to design a simple PLL using a reference architecture, and validate the PLL using PLL Testbench.

Set UP PLL Testbench Model

Open the model simplePLL. The model consists of a Integer N PLL with Dual Modulus Prescaler and PLL Testbench.

open_system('simplePLL.slx')

PLL Specifications and Impairment.

Double click the Integer N PLL with Dual Modulus Prescaler block to open the Block Parameters dialog box. Check that the impairments are enabled in the PFD and Charge Pump tabs. The effective clock divider value in the Prescaler tab is 70 . In the Loop Filter tab, Filter component values are calculated automatically. In the Analysis tab, both Open Loop Analysis and Closed Loop Analysis plots are selected.

Plot Pre-Simulation PLL Loop Dynamics

Click the Plot Loop Dynamics button to view the pre-simulation results.

The closed loop analysis consists of the Pole-Zero Map, Magnitude Response, Step Response, and Impulse Response. The loop bandwidth of the system is 2 MHz.

The open loop analysis consists of Bode plots of the PLL system. The phase margin is 44 degrees.

Modify PLL Testbench for Phase Noise Measurement

Double click the PLL Testbench to open the Block Parameters dialog box. In the Setup tab, check that the Phase noise measurement option is selected.

Plot PLL Phase Noise Profile

Run the simulation for 2.25e-5 s. The simulation results are displayed on the icon of the PLL Testbench. The measured phase noise levels at specific frequency offsets are in accordance with their target values.

Double click the PLL Testbench to open the Block Parameters dialog box. Click the Phot phase noise profile button. The PLL operating frequency is 2.1 GHz and the measured phase noise profile matches with the target profile.