Industry Standard IBIS-AMI Models

Develop industry standard IBIS-AMI models such as PCI, DDR, and Ethernet

SerDes Toolbox™ provides generic examples of how to generate typical industry specific standard models such as peripheral component interconnect (PCI), double data rate (DDR), universal serial bus (USB), and common electrical interconnect (CEI). You can use these examples as a basis of your own design.

Use the SerDes Designer app to design your customized SerDes system, then export the SerDes system to a Simulink^® canvas for further customization of existing control parameters. Once you are satisfied, export the IBIS-AMI models compliant with the standard communication protocols from Simulink. You can also generate industry compliant IBIS-AMI models directly from the app.

Industry Standards

PCIe

PCIe4 Transmitter/Receiver IBIS-AMI Model
This example shows how to create generic PCIe Generation 4 (PCIe4) transmitter and receiver IBIS-AMI models using the library blocks in SerDes Toolbox™.
PCIe5 Transmitter/Receiver IBIS-AMI Model
This example shows how to create IBIS-AMI models for a PCI-Express Generation 5 (PCIe Gen5) transmitter and receiver using the library blocks in SerDes Toolbox™.
PCIe6 Transmitter/Receiver IBIS-AMI Model
This example shows how to create IBIS-AMI models for a PCI-Express Generation 6 (PCIe Gen6) transmitter and receiver using the library blocks in SerDes Toolbox™.

USB

USB 3.1 Transmitter/Receiver IBIS-AMI Model
This example shows how to create generic Universal Serial Bus version 3.1 (USB 3.1) transmitter and receiver IBIS-AMI models using the library blocks in SerDes Toolbox™.
USB4 V2 Transmitter/Receiver IBIS-AMI Model
This example shows how to implement USB4 V2 (80Gbps PAM3) Transmitter and Receiver architectures with SerDes Designer and generate IBIS-AMI models using the library blocks in SerDes Toolbox™.

CEI

CEI-56G-LR Transmitter/Receiver IBIS-AMI Model
Create a generic CEI-56G-LR transmitter and receiver IBIS-AMI models.
CEI-112G-VSR Transmitter/Receiver IBIS-AMI Model
This example shows how to create IBIS-AMI models for an Optical Internetworking Forum (OIF) CEI-112G-VSR (PAM4) transmitter and receiver for chip-to-module applications.

UCI

UCIe 1.0 Transmitter/Receiver IBIS-AMI Model
This example shows how to create IBIS-AMI models for Universal Chiplet Interconnect Express (UCIe) Version 1.0 transmitter and receiver for clock and data using the library blocks in SerDes Toolbox.

DDR

DDR5 Controller Transmitter/Receiver IBIS-AMI Model
Create a generic DDR5 controller transmitter and receiver IBIS-AMI model.
DDR5 SDRAM Transmitter/Receiver IBIS-AMI Model
This example shows how to create generic DDR5 transmitter and receiver IBIS-AMI models using the library blocks in SerDes Toolbox™ and have been Verified by Intel®.
Design DDR5 IBIS-AMI Models to Support Back-Channel Link Training
Create transmitter and receiver AMI models that support link training communication (back-channel).
LPDDR5X IBIS-AMI Models with Clock Forwarding
This example shows how to create IBIS-AMI models for Low Power Double Data Rate 5X (LPDDR 5X) transmitter and receiver for signals including Write-Clock(WCK) and Data(DQ) using the library blocks in SerDes Toolbox.

Featured Examples

ADC IBIS-AMI Model Based on COM

Create IEEE 802.3ck specification ADC-based transmitter and receiver IBIS-AMI models using library blocks in the SerDes Toolbox™ library and custom blocks to model a time-agnostic ADC. The generated models conform to the IBIS-AMI standard. The virtual sampling node, which exists in slicer-based SerDes systems, but does not exist in ADC-based SerDes systems, is emulated to allow for virtual eye diagram generation in the Simulink® and IBIS-AMI simulators for evaluating the channel.

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ADC IBIS-AMI Model Based on COM with Genetic Algorithm Optimization

Improve the performance of SerDes global optimization through the use of genetic algorithms and statistical analysis. The IEEE 802.3ck specification 100G ADC-based COM model serves as a base platform to showcase this optimization technique.

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Architectural 112G PAM4 ADC-Based SerDes Model

Model a 112G PAM4 time-interleaved ADC-Based SerDes.

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Modelling ADC Impairments in SerDes Receiver

Model the effects of ADC Impairments, including offset error, gain error, and differences between interleaved ADCs on the performance of a SerDes Receiver. This example is based on the Architectural 112G PAM4 ADC Based SerDes Example, which explains the model as a whole, its purpose, and theory of operation in more detail.

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Architectural 100G Dual-Summing-Node-DFE PAM4 SerDes Receiver Model

The necessity of managing the adaptive loop update factors to ensure that the numerous adaptive loops don't fight against each other.

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JTOL: Jitter Tolerance Testing

Jitter tolerance testing (JTOL) is a critical part of high-speed communication system characterization and validation. It reveals how well the clock and data recovery unit (CDR) of the system performs as both the magnitude and frequency of injected sinusoidal jitter are varied. When the magnitude and frequency of the sinusoidal jitter (SJ) are within the CDR bandwidth, the CDR is able to track the jitter and compensate for it. As the magnitude and frequency of the jitter increases, the CDR loses the ability to track and system performance suffers.

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