Generación de código HDL en FPGA
Los modelos o subsistemas con requisitos de tiempo de muestreo rápido pueden beneficiarse de la simulación en FPGA. Si dispone de HDL Coder™, puede convertir el modelo de planta de Simscape en un modelo de implementación HDL que puede usar para generar código HDL y desplegarlo en una FPGA. Para desplegar el modelo o subsistema de Simscape en una FPGA:
Utilice la función
sschdladvisorpara iniciar HDL Workflow Advisor de Simscape, que ofrece una guía para el proceso de creación de un modelo de implementación en HDL.Convierta el modelo de implementación a código HDL utilizando la herramienta HDL Workflow Advisor.
Utilice Simulink® Real-Time™ para desplegar el código HDL en una FPGA.
Puede utilizar síntesis de modelos para predecir la unidad de tiempo alcanzable del hardware.
Funciones
sschdladvisor | Open Simscape HDL Workflow Advisor |
simscape.findNonlinearBlocks | Check model for blocks with nonlinear equations |
sschdl.updateRuntimeParameters | Generate updated tunable parameter data file for Simscape model (Desde R2024a) |
sschdl.generateOptimizedModel | Replace Simscape switches and converter blocks with dynamic switches optimized for FPGA deployment (Desde R2024a) |
Temas
- Get Started with Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Simscape™ Hardware-in-the-Loop workflow modeling guidelines and restrictions.
- Linearize a Simscape Model to Prepare for HDL Code Generation
Learn how to linearize a model that uses the Backward Euler solver for HDL deployment.
- Generate HDL Code for FPGA Platforms from Simscape Models
Learn how to convert Simscape models to HDL Code for FPGA Deployment.
- Generate Optimized HDL Implementation Model from Simscape (HDL Coder)
Optimize area and timing of HDL implementation model generated from Simscape by using HDL Coder optimizations.
- Generate and Validate HDL Code for Simscape Model (HDL Coder)
Generate HDL code from Simscape switched linear models.
- Generate HDL Code for Simscape Models with Multiple Networks (HDL Coder)
Split a large Simscape network into multiple networks and generate HDL implementation model.
- Generate HDL Code for Simscape Three-Phase PMSM Drive Containing Averaged Switch (HDL Coder)
Generate HDL code and synthesize the results for a three-phase PMSM Simscape models with converter blocks that have averaged switches and deploy onto the FPGAs.
- Simulate Large Time Steps Using Trapezoidal Rule Solver for Real-Time FPGA Deployment (HDL Coder)
Generate HDL code for a Simscape model by using the Trapezoidal Rule solver and deploy it onto a Speedgoat® FPGA I/O module.
- Generate HDL Code for Simscape Models by Using Dynamic Switch Approximation (HDL Coder)
Generate HDL code and synthesize the results for a three-phase PMSM drive using Dynamic Switch Approximation method.
- Improve FPGA Sampling Frequency of HDL Implementation Model Generated from Simscape Algorithm (HDL Coder)
Oversampling in generated HDL implementation model, and relation between model sample time and sample time of original Simscape algorithm.
- Validate HDL Implementation Model to Simscape Algorithm (HDL Coder)
Validate and resolve simulation mismatch between Simscape algorithm and HDL implementation model.
- Synthesis Results for Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Access synthesis results for Simscape hardware-in-the-loop workflow example models.
Solución de problemas
Resolving Issues with Nonlinearities
Troubleshoot simulation and code generation issues associated with nonlinearities.
Troubleshooting Real-Time Hardware Deployment Issues in Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Troubleshoot real-time hardware deployment issues in Simscape Hardware-in-the-Loop workflow.
Troubleshoot Validation Errors in Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Troubleshoot validation mismatches in Simscape Hardware-in-the-Loop workflow.
Ejemplos destacados
Generate Optimized Simscape Three-Phase PMSM Drive Model for Real-Time FPGA HIL Deployment
Optimize three-phase PMSM model from a Simscape model for HDL code generation and FPGA deployment.
Generate HDL Code for Two-Speed Transmission Model Containing Mode Charts
Generate HDL code and synthesize the results for a two-speed transmission model with braking that contains mode charts.
Rectificador de onda completa tipo puente
Este ejemplo muestra cómo dimensionar un condensador para una carga concreta en un transformador que convierte de 120 VCA a 12 VCC. El sistema está modelado como un transformador de CA ideal más un rectificador de onda completa tipo puente.
