Mux
Combine input signals of same data type and complexity into virtual vector
- Library:
Simulink / Commonly Used Blocks
Simulink / Signal Routing
HDL Coder / Commonly Used Blocks
HDL Coder / Signal Routing
Description
The Mux block combines inputs with the same data type and complexity into a vector output. The output mux signal is flat, even if you create the mux signal from other mux signals. However, you can use multiple Mux blocks to create a mux signal in stages.
A mux signal simplifies the visual appearance of a model by combining two or more signal lines into one line. Mux signals do not affect simulation or code generation.
Tip
If inputs have different data types or complexity, use a Bus Creator block to visually group the signals in a virtual bus. For more information, see Types of Composite Signals.
Ports
Input
Port_1
— Input signal to include in mux signal
scalar | vector
Input signal to include in the mux signal, specified as a scalar or vector.
The input signals for a Mux block can be any combination of scalars and vectors, but they must have the same data type and complexity.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
| enumerated
| image
Complex Number Support: Yes
Output
Port_1
— Output mux signal
vector
Output mux signal composed of the combined input signals, returned as a vector.
The elements of the output mux signal take their order from the port order of the input signals. For a description of the port order for various block orientations, see Port Location After Rotating or Flipping.
Data Types: single
| double
| half
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
| enumerated
| image
Parameters
Number of inputs
— Number of input signals
2 (default) | scalar | vector | cell array | comma-separated list of signal names
The number of input signals, specified as a scalar, vector, cell array, or comma-separated list of signal names. Some of these formats allow you to specify the signal names and sizes, as described by the following table.
Format | Block Behavior |
---|---|
Scalar | The number of inputs to the Mux block. When you use this format, the block
accepts scalar or vector signals of any size.
Simulink® assigns each input the name
|
Vector | The length of the vector specifies the number of inputs. Each element specifies the size of the corresponding input. A positive value
specifies that the corresponding port can accept only
vectors of that size. For example, |
Cell array | The length of the cell array specifies the number of inputs. The value of each cell specifies the size of the corresponding input. A scalar value
|
Comma-separated list of signal names | A list of signal names separated by commas.
Simulink assigns each name to the corresponding
port and signal. For example, if you enter
|
Tip
If you specify a scalar for the Number of inputs parameter and all of the input ports are connected, as you draw a new signal line close to input side of a Mux block, Simulink adds a port and updates the parameter.
Programmatic Use
Block Parameter:
Inputs |
Type: scalar, vector, cell array, comma-separated list of signal names |
Values: integer, vector of port sizes, cell array, comma-separated list of signal names |
Default:
'2' |
Display option
— Block icon appearance
bar
(default) | signal
| none
Block icon appearance, specified as bar
,
signal
, or
none
.
bar
— Displays no textsignal
— Displays the input signal namesnone
— Displays the type of block (Mux)
Resize the block as necessary to fit the text on the block icon.
Programmatic Use
Block Parameter:
DisplayOption |
Type: character vector |
Values:
'bar'
'signals'
'none' 'bar' |
Default:
'bar' |
Model Examples
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Actual data type or capability support depends on block implementation.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
This block supports code generation for complex signals.
Buses are not supported for HDL code generation.
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
Actual data type or capability support depends on block implementation.
Version History
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