First read transfer latency (clocks)

Delay, in clock cycles, between a read request and the start of a transfer

Model Configuration Pane: Target hardware resources / FPGA design (PS mem controllers)

Description

Specify the delay, in clock cycles, between a read request and the start of a transfer.

This delay is the number of clock cycles between making a request to the memory controller and until it returns a response. It is reflected in the Logic Analyzer waveforms as the time that the memory controller state remains as BurstAccepted. For more information about viewing waveforms in simulation, see Buffer and Burst Waveforms.

To set this value, measure the clock cycles between the burst-request and start of transfer on your board. For instructions for extracting this information from a hardware execution, see Configuring and Querying the AXI Interconnect Monitor.

Settings

5 (default)

Default: 5

Programmatic Use

Parameter:

Type:

Values: 5

Default: 5

Version History

Introduced in R2019a