Similar to the memory performance plots generated in simulation, you can collect memory interconnect traffic information from a design running on the FPGA. You can then generate similar performance and latency plots. You can also capture transaction information to view in the Logic Analyzer tool. Use these memory interconnect metrics to monitor real memory performance, debug and improve the design, and compare them against the memory performance obtained in simulation.
To include an AXI interconnect monitor (AIM) IP in your design, in the configuration parameters of the model, select the Include AXI interconnect monitor option under Hardware Implementation > Target hardware resources > FPGA design (debug). The AXI interconnect monitor IP collects information from the design while it is running on the FPGA. This information can be queried from MATLAB® by using the JTAG connection. All memory masters in your FPGA are connected to the AXI interconnect monitor IP. These masters can include Memory Channel and Memory Traffic Generator blocks that you generated HDL code for or other masters in your design.
The SoC Builder generates a script that collects and displays the metrics returned by the AXI interconnect monitor. The generated plots are similar to the plots of memory performance in simulation, displaying bandwidth, number of bursts, and transaction latencies. You can also modify the script to collect and display memory control signal waveforms similar to the memory transaction waveforms from simulation. For information on the simulation memory performance tools, see Simulation Performance Plots and Buffer and Burst Waveforms.
For an example, see Analyze Memory Bandwidth Using Traffic Generators, which shows how to monitor memory performance in both simulation and when running on the FPGA.
The script generated by the SoC Builder tool uses the JTAG connection to enable any traffic generators in your design, and then samples the memory performance information from the AXI interconnect monitor IP as fast as it can. The sampling interval depends on the JTAG latency, which is typically from 10 ms to 20 ms. The script then displays plots similar to the performance plots from the Memory Controller block in your simulation. The plot displays the bandwidth, number of bursts, and transaction latency for each master.
The JTAG master itself is not connected to the AXI interconnect monitor. Therefore, the hardware diagnostics do not include the memory usage plots for test-bench-only masters that initialize the memory with predetermined data.
The latency is an average of the time from the start of the burst request to the first data transfer, over the sampling interval. It is expressed as an absolute time. To convert the latency to clock cycles, divide the time value by the clock period of the FPGA.
You can also modify the generated script to configure the AXI interconnect monitor to collect event data for each burst transaction. You can view these events in the Logic Analyzer waveform viewer to examine arbitration behavior. Specify the number of transactions to capture, Trace capture depth, in the configuration parameters of the model, under Hardware Implementation > Target hardware resources > FPGA design (debug).
The waveforms show the event type (
BurstDone) and these parameters of the burst transaction:
MasterID –– ID number of the memory master that made
DataWidth –– Data width in bits
BurstLength –– Number of data words in the burst
BurstsTransferred –– Number of bursts in this request
(valid only with
BytesTransferred –– Number of bytes in this request
(valid only with
You can compare these waveforms with the waveforms captured from your Memory Controller block in simulation.
The AXI interconnect monitor (AIM) is an IP core that collects
performance metrics for an AXI-based FPGA design. Create an
object to set up and configure the AIM IP, and use the
socMemoryProfiler object to retrieve and display the data.
For an example of how to configure and query the AIM IP in your design using
MATLAB as AXI Master, see Analyze Memory Bandwidth Using Traffic Generators. Specifically, review the
soc_memory_traffic_generator_axi_master.m script that configures
and monitors the design on the device.
The performance monitor can collect two types of data. Choose Profile mode to collect average transaction latency, and counts of bytes and bursts. In this mode, you can launch a performance plot tool, and then configure the tool to plot bandwidth, burst count, and transaction latency. Choose Trace mode to collect detailed memory transaction event data and view the data as waveforms.
perfMonMode = 'Profile'; % or 'Trace'
obtain diagnostic performance metrics from your generated FPGA design, you must set
up a JTAG connection to the device from MATLAB.Load a
.mat file that contains structures derived
from the board configuration parameters. This file was generated by the SoC
Builder tool. These structures describe the memory interconnect and
masters configuration such as buffer sizes and addresses. Use the
socHardwareBoard object to set up
the JTAG connection.
load('soc_memory_traffic_generator_zc706_aximaster.mat'); hwObj = socHardwareBoard('Xilinx Zynq ZC706 evaluation kit','Connect',false); AXIMasterObj = socAXIMaster(hwObj);
socIPCoreobject provides a function that performs this initialization. Next, set up a
socMemoryProfilerobject to gather the metrics.
apmCoreObj = socIPCore(AXIMasterObj,perf_mon,'PerformanceMonitor','Mode',perfMonMode); initialize(apmCoreObj); profilerObj = socMemoryProfiler(hwObj,apmCoreObj);
Retrieve performance metrics or signal data from a design running on the FPGA, use
socMemoryProfiler object functions.
'Profile' mode, call the
collectMemoryStatistics function in a loop.
NumRuns = 100; for n = 1:NumRuns collectMemoryStatistics(profilerObj); end
'Trace' mode, call the
collectMemoryStatistics function once. This function stops the IP
from writing transactions into the FIFO in the AXI interconnect
monitor IP, although the transactions continue on the interconnect. Set
the size of the transaction FIFO, Trace capture depth, in the
configuration parameters of the model, under Hardware Implementation > Target hardware resources > FPGA design (debug).
Visualize the performance data, by using the
plotMemoryStatistics function. In
this function launches a performance plot tool, and you can configure the tool to
plot bandwidth, burst count, and average transaction latency. In
'Trace' mode, this function opens the Logic
Analyzer tool to view burst transaction event data.