Plot performance data obtained from AXI interconnect monitor
visualizations of the performance data from the AXI interconnect monitor IP
running on your hardware board. The
profiler object represents a
connection to that IP. When the AXI interconnect monitor is configured in
'Profile' mode, this function launches a performance plot tool. You can
configure the tool to plot bandwidth, burst count, and average transaction latency. In
'Trace' mode, this function opens the Logic Analyzer to
view detailed memory transaction event data.
Configure and Query AXI Interconnect Monitor
The AXI interconnect monitor (AIM) is an IP core that collects
performance metrics for an AXI-based FPGA design. Create an
object to setup and configure the AIM IP, and use the
socMemoryProfiler object to retrieve and display the data.
For an example of how to configure and query the AIM IP in your design using
MATLAB® as AXI Master, see Analyze Memory Bandwidth Using Traffic Generators. Specifically, review the
soc_memory_traffic_generator_axi_master.m script that
configures and monitors the design on the device.
The performance monitor can collect two types of data. Choose Profile mode to collect average transaction latency and counts of bytes and bursts. In this mode, you can launch a performance plot tool, and then configure the tool to plot bandwidth, burst count, and transaction latency. Choose Trace mode to collect detailed memory transaction event data and view the data as waveforms.
Mode = 'Profile'; % or 'Trace'
obtain diagnostic performance metrics from your generated FPGA design, you must set
up a JTAG connection to the device from MATLAB. Load a
.mat file that contains structures derived
from the board configuration parameters. This file was generated by the SoC
Builder tool. These structures describe the memory interconnect and
masters configuration such as buffer sizes and addresses. Use the
socHardwareBoard object to set up
the JTAG connection.
load('soc_memory_traffic_generator_zc706_aximaster.mat'); hwObj = socHardwareBoard('Xilinx Zynq ZC706 evaluation kit','Connect',false); AXIMasterObj = socAXIMaster(hwObj);
apmCoreObj = socIPCore(AXIMasterObj,perf_mon,'PerformanceMonitor','Mode',Mode); initialize(apmCoreObj); profilerObj = socMemoryProfiler(hwObj,apmCoreObj);
Retrieve performance metrics or signal data from a design running on the FPGA by
socMemoryProfiler object functions.
'Profile' mode, call the
collectMemoryStatistics function in a loop.
NumRuns = 100; for n = 1:NumRuns collectMemoryStatistics(profilerObj); end
'Trace' mode, call the
collectMemoryStatistics function once. This function stops the IP
from writing transactions into the FIFO in the AXI interconnect
monitor IP, although the transactions continue on the interconnect. Set
the size of the transaction FIFO, Trace capture depth, in the
configuration parameters of the model, under Hardware Implementation > Target hardware resources > FPGA design (debug).
Visualize the performance data by using the
plotMemoryStatistics function. In
this function launches a performance plot tool, and you can configure the tool to
plot bandwidth, burst count, and average transaction latency. In
'Trace' mode, this function opens the Logic
Analyzer tool to view burst transaction event data.
Introduced in R2019a